makefile 1.65 KB
Newer Older
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
1
2
3
## ----------------------------------------------------------------------------
## Script     : makefile
## ----------------------------------------------------------------------------
4
## Author     : Johann Faerber, Friedrich Beckmann
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
5
6
## Company    : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
7
8
9
## Description: This makefile allows automating design flow with Quartus,
##              it is based on a design directory structure described in 
##              ../makefile
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
10
11
12
13
14
## ----------------------------------------------------------------------------

###################################################################
# Project Configuration: 
#
15
16
17
18
19
20
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite: 
#   - mandatory design directory structure (see end of file)
#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
21
###################################################################
22

Johann Faerber's avatar
Johann Faerber committed
23
24
SIM_PROJECT_NAME = binto7segment
PROJECT = de1_$(SIM_PROJECT_NAME)
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
25

26
27
28
29
30
31
32
33
34
35
36
37
38
39
# Prototype Board FPGA family and device settings
# DE1
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6

Johann Faerber's avatar
Johann Faerber committed
40
41
# Here the VHDL files for synthesis are defined. 
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
42

Johann Faerber's avatar
Johann Faerber committed
43
44
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
45
../../src/$(PROJECT)_structure.vhd
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
46

Johann Faerber's avatar
Johann Faerber committed
47
include ../makefile
Friedrich Beckmann's avatar
first  
Friedrich Beckmann committed
48
49