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## ----------------------------------------------------------------------------
## Script     : makefile
## ----------------------------------------------------------------------------
## Author     : Johann Faerber
## Company    : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## ----------------------------------------------------------------------------

###################################################################
# Project Configuration: 
#
# Prerequisite: mandatory design directory structure (see end of file)
#
# - modify and copy it to sim/(PROJECT)/makefile
# - Specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
###################################################################

PROJECT = binto7segment
SOURCE_FILES = \
../../src/binto7segment_stimuli.vhd \
../../src/binto7segment_truthtable.vhd \
../../src/de1_binto7segment_structure.vhd \
../../src/t_$(PROJECT).vhd


###################################################################
# Main Targets
#
###################################################################

help:
	@echo '"make" does intentionally nothing. Type:'
	@echo '  "make clean" to remove all generated files'
	@echo '  "make project" to create a new modelsim project'
	@echo '  "make modelsim" to start modelsim with graphical user interface'
	@echo '  "make sim" to start modelsim gui with the top testbench of the project'
	@echo '  "make compile" to compile all VHDL sources in batch mode'

project : 
	# create modelsim project
	vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); quit -f"
	# assign VHDL design files
	for source_file in $(SOURCE_FILES); do \
		vsim -c -do "project open  $(PROJECT); project addfile $$source_file; quit -f" ; \
	done
	
compile:
	vsim -c -do "project open $(PROJECT); project calculateorder; quit -f"

modelsim:
	vsim -do "project open $(PROJECT); " &

sim:
	vsim -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;" &

clean:
	rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work

## ----------------------------------------------------------------------------
## Description: 
## ------------
## assumes the following design directory structure as prerequisite
## 
## DigitaltechnikPraktikum
## |   
## +---src
## |       and2gate_equation.vhd
## |       de1_mux2to1_structure.vhd
## |       invgate_equation.vhd
## |       mux2to1_structure.vhd
## |       or2gate_equation.vhd
## |       t_mux2to1.vhd
## |       
## +---pnr
## |   +---de1_mux2to1
## |           makefile
## |           de1_mux2to1.qpf
## |           de1_mux2to1.qpf
## |
## +---scripts
## |       quartus_project_settings.tcl
## |       makefile.quartus_template
## |       makefile.modelsim_template
## |       de1_mux2to1_pins.tcl
## |       modelsim_project_settings.tcl
## |       modelsim.ini
## |       de1_pin_assignments_minimumio.csv
## |       de1_pin_assignments_minimumio.tcl
## |       
## \---sim
##     +---mux2to1
##             makefile
##             mux2to1.mpf
##             modelsim.ini
## 
## ----------------------------------------------------------------------------
## Modifications: makefile template from Altera Quartus scripting modified:
## --------------
##              - added help target
##              - make project to create a new modelsim project
##              - make modelsim to start modelsim with graphical user interface
##              - make sim to start modelsim gui with the top testbench of the project
##              - make compile to compile all VHDL sources in batch mode
## ----------------------------------------------------------------------------
## Revisions:
## ----------
## $Id:$
## ----------------------------------------------------------------------------