seqdet_rtl.vhd

library ieee;
use ieee.std_logic_1164.all;

entity seqdet is 
port ( clk         : in  std_ulogic;
       rst_n       : in  std_ulogic;       
       ser_i       : in  std_ulogic;
       done_o      : out  std_ulogic);  
end entity;

architecture rtl of seqdet is
  
begin
  
end architecture rtl;