more explicit type cast in the 4 bit adder

src/add4_rtl.vhd

@@ -9,10 +9,21 @@ port ( a_i   : in      std_ulogic_vector(3 downto 0);
        y_o   : out     std_ulogic_vector(3 downto 0));    
 end entity;
 
-architecture rtl of add4 is 
+architecture rtl of add4 is
+
+  signal a,b,sum : unsigned(3 downto 0);
 
 begin
-  
-  y_o <= std_ulogic_vector(unsigned(a_i) + unsigned(b_i)); 
+
+  -- Typecast of the std_ulogic_vector type inputs to type unsigned
+  a <= unsigned(a_i);
+  b <= unsigned(b_i);
+
+  -- Add
+  sum <= a + b;
+
+  -- Typecast the result of the additon from unsigned to std_ulogic_vector
+  -- for the output.
+  y_o <= std_ulogic_vector(sum);
  
 end architecture rtl;