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Friedrich Beckmann
digitaltechnikpraktikum
Commits
00159813
Commit
00159813
authored
Mar 20, 2021
by
Friedrich Beckmann
Browse files
more explicit type cast in the 4 bit adder
parent
229ae03c
Changes
1
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Inline
Side-by-side
src/add4_rtl.vhd
View file @
00159813
...
...
@@ -9,10 +9,21 @@ port ( a_i : in std_ulogic_vector(3 downto 0);
y_o
:
out
std_ulogic_vector
(
3
downto
0
));
end
entity
;
architecture
rtl
of
add4
is
architecture
rtl
of
add4
is
signal
a
,
b
,
sum
:
unsigned
(
3
downto
0
);
begin
y_o
<=
std_ulogic_vector
(
unsigned
(
a_i
)
+
unsigned
(
b_i
));
-- Typecast of the std_ulogic_vector type inputs to type unsigned
a
<=
unsigned
(
a_i
);
b
<=
unsigned
(
b_i
);
-- Add
sum
<=
a
+
b
;
-- Typecast the result of the additon from unsigned to std_ulogic_vector
-- for the output.
y_o
<=
std_ulogic_vector
(
sum
);
end
architecture
rtl
;
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