Commit 0a6c266d authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

added makefiles for simulation

parent 38d026a0
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## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# assign variable PROJECT with the top level project name
#
# Prerequisite:
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = ledsw
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author(s) : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure shown at
## the end of this file.
## ----------------------------------------------------------------------------
###################################################################
# Main Targets
#
###################################################################
help:
@echo '"make" does intentionally nothing. Type:'
@echo ' "make mproject" to create a new modelsim project'
@echo ' "make compile" to compile all VHDL sources in batch mode'
@echo ' "make modelsim" to start modelsim with graphical user interface'
@echo ' "make sim" to start modelsim gui with the top testbench of the project'
@echo ' "make clean" to remove all generated files'
mproject : $(PROJECT).mpf
$(PROJECT).mpf : $(SOURCE_FILES)
# create modelsim project
rm -rf ./modelsim_sources.tcl
for source_file in $(SOURCE_FILES); do \
echo project addfile $$source_file >> modelsim_sources.tcl; \
done
vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f"
compile: ./work/_vmake
./work/_vmake: $(PROJECT).mpf
vsim -c -do "project open $(PROJECT); project calculateorder; quit -f"
modelsim: ./work/_vmake
# vsim -i $(PROJECT) &
vsim -i -do "project open $(PROJECT); " &
sim: ./work/_vmake
vsim -i -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;" &
clean:
rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work modelsim_sources.tcl
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author(s) : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure shown at
## the end of this file.
## ----------------------------------------------------------------------------
###################################################################
# Main Targets
#
###################################################################
help:
@echo '"make" does intentionally nothing. Type:'
@echo ' "make mproject" to create a new modelsim project only'
@echo ' "make compile" to compile all VHDL sources in batch mode'
@echo ' "make modelsim" to start modelsim with graphical user interface'
@echo ' "make sim" to start modelsim gui with the top testbench of the project'
@echo ' "make clean" to remove all generated files'
mproject : $(PROJECT).mpf
$(PROJECT).mpf : $(SOURCE_FILES)
# create modelsim project
rm -rf ./modelsim_sources.tcl
for source_file in $(SOURCE_FILES); do \
echo project addfile $$source_file >> modelsim_sources.tcl; \
done
vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f"
compile: ./work/_vmake
./work/_vmake: $(PROJECT).mpf
vsim -c -do "project open $(PROJECT); project calculateorder; quit -f"
modelsim: $(PROJECT).mpf
vsim -i -do "project open $(PROJECT)" &
sim: ./work/_vmake
vsim -i -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;" &
clean:
rm -rf *~ *.mpf *.mti *.ini *.wlf wlf* transcript work modelsim_sources.tcl
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Testbench for the first switch/led module
-- The switches are switched...
entity t_ledsw is
end;
architecture tbench of t_ledsw is
-- This is the component declaration
component ledsw
port (
SW: in std_ulogic_vector(9 downto 0);
LEDR: out std_ulogic_vector(9 downto 0)
);
end component;
-- Signal declaration for the switches and the leds
signal switches, redleds : std_ulogic_vector(9 downto 0);
begin
-- Here the device under test is instantiated
-- The ledsw circuit is connected to the signals in the testbench
ledsw_i0 : ledsw
port map (
SW => switches,
LEDR => redleds);
-- This is the process where the switches are switched. This process is not synthesizable because
-- of the wait statement.
schalter : process
begin
wait for 1 us;
switches <= "0000000001";
wait for 3 us;
switches <= "1000000000";
wait for 2 us;
switches <= "0000000001";
wait for 5 us;
switches <= "1000000000";
wait; -- wait forever
end process schalter;
end; -- architecture
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