Commit 0c45fdda authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

add de1_sram_echo

The de1_sram_echo project uses the external asynchronous sram
on the Altera DE1 board for the echo machine.
parent 9b619a81
# Pin Configuration
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY0
set_location_assignment PIN_A3 -to I2C_SCLK
set_location_assignment PIN_B3 -to I2C_SDAT
set_location_assignment PIN_A6 -to AUD_ADCLRCK
set_location_assignment PIN_B6 -to AUD_ADCDAT
set_location_assignment PIN_A5 -to AUD_DACLRCK
set_location_assignment PIN_B5 -to AUD_DACDAT
set_location_assignment PIN_B4 -to AUD_XCK
set_location_assignment PIN_A4 -to AUD_BCLK
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_R17 -to LEDR[9]
set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
set_location_assignment PIN_V11 -to SRAM_ADDR[8]
set_location_assignment PIN_W11 -to SRAM_ADDR[9]
set_location_assignment PIN_R11 -to SRAM_ADDR[10]
set_location_assignment PIN_T11 -to SRAM_ADDR[11]
set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
set_location_assignment PIN_U10 -to SRAM_ADDR[13]
set_location_assignment PIN_R10 -to SRAM_ADDR[14]
set_location_assignment PIN_T7 -to SRAM_ADDR[15]
set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
set_location_assignment PIN_AB5 -to SRAM_CE_N
set_location_assignment PIN_AA6 -to SRAM_DQ[0]
set_location_assignment PIN_AB6 -to SRAM_DQ[1]
set_location_assignment PIN_AA7 -to SRAM_DQ[2]
set_location_assignment PIN_AB7 -to SRAM_DQ[3]
set_location_assignment PIN_AA8 -to SRAM_DQ[4]
set_location_assignment PIN_AB8 -to SRAM_DQ[5]
set_location_assignment PIN_AA9 -to SRAM_DQ[6]
set_location_assignment PIN_AB9 -to SRAM_DQ[7]
set_location_assignment PIN_Y9 -to SRAM_DQ[8]
set_location_assignment PIN_W9 -to SRAM_DQ[9]
set_location_assignment PIN_V9 -to SRAM_DQ[10]
set_location_assignment PIN_U9 -to SRAM_DQ[11]
set_location_assignment PIN_R9 -to SRAM_DQ[12]
set_location_assignment PIN_W8 -to SRAM_DQ[13]
set_location_assignment PIN_V8 -to SRAM_DQ[14]
set_location_assignment PIN_U8 -to SRAM_DQ[15]
set_location_assignment PIN_Y7 -to SRAM_LB_N
set_location_assignment PIN_T8 -to SRAM_OE_N
set_location_assignment PIN_W7 -to SRAM_UB_N
set_location_assignment PIN_AA10 -to SRAM_WE_N
SIM_PROJECT_NAME = de1_sram_echo
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
PROJECT = de1_sram_echo
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/sram_beh.vhd \
../../src/t_$(PROJECT).vhd
include ../makefile
SYN_SOURCE_FILES = \
../../src/adcintf.vhd \
../../src/bclk.vhd \
../../src/dacintf.vhd \
../../src/fsgen.vhd \
../../src/i2c_sub.vhd \
../../src/i2c.vhd \
../../src/i2c_write.vhd \
../../src/mclk.vhd \
../../src/sram_echo.vhd \
../../src/audio.vhd \
../../src/de1_sram_echo.vhd
--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera;
use altera.altera_primitives_components.all;
entity de1_sram_echo is
port (
CLOCK_50: in std_ulogic;
KEY0: in std_ulogic;
I2C_SCLK: out std_ulogic;
I2C_SDAT: inout std_logic;
AUD_ADCLRCK: out std_ulogic;
AUD_ADCDAT: in std_ulogic;
AUD_DACLRCK: out std_ulogic;
AUD_DACDAT: out std_ulogic;
AUD_XCK: out std_ulogic;
AUD_BCLK: out std_ulogic;
SRAM_ADDR: out std_ulogic_vector(17 downto 0);
SRAM_CE_N: out std_ulogic;
SRAM_WE_N: out std_ulogic;
SRAM_OE_N: out std_ulogic;
SRAM_UB_N: out std_ulogic;
SRAM_LB_N: out std_ulogic;
SRAM_DQ: inout std_logic_vector(15 downto 0);
LEDR: out std_ulogic_vector(9 downto 0));
end;
architecture struct of de1_sram_echo is
component audio is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
i2c_sclk_o : out std_ulogic;
i2c_dat_i : in std_ulogic;
i2c_dat_o : out std_ulogic;
aud_adclrck_o : out std_ulogic;
aud_adcdat_i : in std_ulogic;
aud_daclrck_o : out std_ulogic;
aud_dacdat_o : out std_ulogic;
aud_xck_o : out std_ulogic;
aud_bclk_o : out std_ulogic;
adc_data_o : out std_ulogic_vector(15 downto 0);
adc_valid_o : out std_ulogic;
dac_data_i : in std_ulogic_vector(15 downto 0);
dac_strobe_o : out std_ulogic);
end component;
component sram_echo is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
adc_valid_i : in std_ulogic;
adc_data_i : in std_ulogic_vector(15 downto 0);
dac_data_o : out std_ulogic_vector(15 downto 0);
sram_addr_o : out std_ulogic_vector(17 downto 0);
sram_wdata_o : out std_ulogic_vector(15 downto 0);
sram_rdata_i : in std_ulogic_vector(15 downto 0);
sram_trien_o : out std_ulogic;
sram_we_no : out std_ulogic;
sram_oe_no : out std_ulogic);
end component;
signal clk, reset_n : std_ulogic;
signal i2c_dat_o : std_ulogic;
signal i2c_dat_i : std_ulogic;
signal adc_valid : std_ulogic;
signal dac_strobe : std_ulogic;
signal dac_data, adc_data : std_ulogic_vector(15 downto 0);
signal sram_wdata : std_ulogic_vector(15 downto 0);
signal sram_rdata : std_ulogic_vector(15 downto 0);
signal sram_trien : std_ulogic;
begin
reset_n <= KEY0;
clk <= CLOCK_50;
audio_i0 : audio
port map (
clk_i => clk,
reset_ni => reset_n,
i2c_sclk_o => I2C_SCLK,
i2c_dat_i => i2c_dat_i,
i2c_dat_o => i2c_dat_o,
aud_adclrck_o => AUD_ADCLRCK,
aud_adcdat_i => AUD_ADCDAT,
aud_daclrck_o => AUD_DACLRCK,
aud_dacdat_o => AUD_DACDAT,
aud_xck_o => AUD_XCK,
aud_bclk_o => AUD_BCLK,
adc_data_o => adc_data,
adc_valid_o => adc_valid,
dac_data_i => dac_data,
dac_strobe_o => dac_strobe);
sram_echo_i0 : sram_echo
port map (
clk_i => clk,
reset_ni => reset_n,
adc_valid_i => adc_valid,
adc_data_i => adc_data,
dac_data_o => dac_data,
sram_addr_o => SRAM_ADDR,
sram_wdata_o => sram_wdata,
sram_rdata_i => SRAM_rdata,
sram_trien_o => sram_trien,
sram_we_no => SRAM_WE_N,
sram_oe_no => SRAM_OE_N);
SRAM_DQ <= std_logic_vector(sram_wdata) when sram_trien = '1' else
(others => 'Z');
sram_rdata <= std_ulogic_vector(SRAM_DQ);
SRAM_CE_N <= '0';
SRAM_UB_N <= '0';
SRAM_LB_N <= '0';
LEDR(9 downto 0) <= std_ulogic_vector(abs(signed(dac_data(15 downto 6))));
-- i2c has an open-drain ouput
i2c_dat_i <= I2C_SDAT;
i2c_data_buffer_i : OPNDRN
port map (a_in => i2c_dat_o, a_out => I2C_SDAT);
end; -- architecture
--Copyright 2021 Friedrich Beckmann, Hochschule Augsburg
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sram_echo is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
adc_valid_i : in std_ulogic;
adc_data_i : in std_ulogic_vector(15 downto 0);
dac_data_o : out std_ulogic_vector(15 downto 0);
sram_addr_o : out std_ulogic_vector(17 downto 0);
sram_wdata_o : out std_ulogic_vector(15 downto 0);
sram_rdata_i : in std_ulogic_vector(15 downto 0);
sram_trien_o : out std_ulogic;
sram_we_no : out std_ulogic;
sram_oe_no : out std_ulogic
);
end;
architecture rtl of sram_echo is
signal addr : unsigned(17 downto 0);
signal addr_inc : std_ulogic;
signal rdata_reg_en : std_ulogic;
signal wdata_reg_en : std_ulogic;
type state_t is (IDLE, STORE, RWT, WRITE1, WRITE2, WRITE3, WRT);
signal cstate, nstate : state_t;
begin
addr <= (others => '0') when reset_ni = '0' else
addr + 1 when rising_edge(clk_i) and addr_inc = '1';
sram_addr_o <= std_ulogic_vector(addr);
sram_wdata_o <= (others => '0') when reset_ni = '0' else
adc_data_i when wdata_reg_en = '1' and rising_edge(clk_i);
dac_data_o <= (others => '0') when reset_ni = '0' else
sram_rdata_i when rdata_reg_en = '1' and rising_edge(clk_i);
cstate <= IDLE when reset_ni = '0' else nstate when rising_edge(clk_i);
process (cstate, adc_valid_i)
begin
rdata_reg_en <= '0';
wdata_reg_en <= '0';
addr_inc <= '0';
sram_we_no <= '1';
sram_oe_no <= '1';
sram_trien_o <= '0';
nstate <= IDLE;
case cstate is
when IDLE =>
sram_oe_no <= '0';
if adc_valid_i = '1' then
nstate <= STORE;
wdata_reg_en <= '1';
end if;
when STORE =>
sram_oe_no <= '0';
rdata_reg_en <= '1';
nstate <= RWT;
when RWT =>
nstate <= WRITE1;
when WRITE1 =>
sram_trien_o <= '1';
sram_we_no <= '0';
nstate <= WRITE2;
when WRITE2 =>
sram_trien_o <= '1';
sram_we_no <= '0';
nstate <= WRITE3;
when WRITE3 =>
sram_trien_o <= '1';
nstate <= WRT;
when WRT =>
addr_inc <= '1';
nstate <= IDLE;
end case;
end process;
end; -- architecture
--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity t_de1_audio is
end;
architecture tbench of t_de1_audio is
component de1_sram_echo is
port (
CLOCK_50 : in std_ulogic;
KEY0 : in std_ulogic;
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_ulogic;
AUD_ADCLRCK : out std_ulogic;
AUD_ADCDAT : in std_ulogic;
AUD_DACLRCK : out std_ulogic;
AUD_DACDAT : out std_ulogic;
AUD_XCK : out std_ulogic;
AUD_BCLK : out std_ulogic;
SRAM_ADDR : out std_ulogic_vector(17 downto 0);
SRAM_CE_N : out std_ulogic;
SRAM_WE_N : out std_ulogic;
SRAM_OE_N : out std_ulogic;
SRAM_UB_N : out std_ulogic;
SRAM_LB_N : out std_ulogic;
SRAM_DQ : inout std_logic_vector(15 downto 0);
LEDR : out std_ulogic_vector(9 downto 0)
);
end component;
component sram is
port (ce_n : in std_ulogic;
we_n : in std_ulogic;
oe_n : in std_ulogic;
ub_n : in std_ulogic;
lb_n : in std_ulogic;
d : inout std_logic_vector(15 downto 0);
a : in std_ulogic_vector(17 downto 0));
end component;
signal clk, reset_n : std_ulogic;
signal ledr : std_ulogic_vector(9 downto 0);
signal i2c_clk, i2c_dat : std_ulogic;
signal key0 : std_ulogic;
signal aud_adclrck, aud_adcdat, aud_daclrck : std_ulogic;
signal aud_dacdat, aud_xck, aud_bclk : std_ulogic;
signal simrun : boolean := true;
signal phase : real := 0.0;
signal test_tone : real;
signal test_tone_quantized : signed(15 downto 0);
signal bit_count : integer range 0 to 31;
-- SRAM
signal sram_addr : std_logic_vector(17 downto 0);
signal sram_ce_n : std_ulogic;
signal sram_we_n : std_ulogic;
signal sram_oe_n : std_ulogic;
signal sram_ub_n : std_ulogic;
signal sram_lb_n : std_ulogic;
signal sram_dq : std_logic_vector(15 downto 0);
begin
de1_sram_echo_i0 : de1_sram_echo
port map (
CLOCK_50 => clk,
KEY0 => reset_n,
I2C_SCLK => i2c_clk,
I2C_SDAT => i2c_dat,
AUD_ADCLRCK => aud_adclrck,
AUD_ADCDAT => aud_adcdat,
AUD_DACLRCK => aud_daclrck,
AUD_DACDAT => aud_dacdat,
AUD_XCK => aud_xck,
AUD_BCLK => aud_bclk,
SRAM_ADDR => sram_addr,
SRAM_CE_N => sram_ce_n,
SRAM_WE_N => sram_we_n,
SRAM_OE_N => sram_oe_n,
SRAM_UB_N => sram_ub_n,
SRAM_LB_N => sram_lb_n,
SRAM_DQ => sram_dq,
LEDR => ledr);
clock_p : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if not simrun then
wait;
end if;
end process clock_p;
simrun <= false after 5 ms;
reset_p : process
begin
reset_n <= '0';
wait for 15 us;
reset_n <= '1';
wait;
end process reset_p;
aud_adcdat <= test_tone_quantized(bit_count mod 16);
-- Test tone generator for simulating the ADC from the audio codec
phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck);
test_tone <= sin(2*3.14*phase);
test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16);
bit_count <= 31 when falling_edge(aud_daclrck) else
0 when bit_count = 0 else
bit_count - 1 when falling_edge(aud_bclk);
sram_i0 : sram
port map (
ce_n => sram_ce_n,
we_n => sram_we_n,
oe_n => sram_oe_n,
ub_n => sram_ub_n,
lb_n => sram_lb_n,
d => sram_dq,
a => sram_addr);
end; -- architecture
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