added flipflop in sim and pnr

pnr/de1_flipflop/de1_flipflop_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R22 -to KEY[0] 
+set_location_assignment PIN_R21 -to KEY[1] 
+set_location_assignment PIN_T22 -to KEY[2] 
+set_location_assignment PIN_T21 -to KEY[3] 
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]

pnr/de1_flipflop/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+
+SIM_PROJECT_NAME = de1_flipflop
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

sim/de1_flipflop/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+PROJECT = de1_flipflop
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+
+

sim/de1_flipflop/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/de1_flipflop_rtl.vhd 
+
+# do not delete this line
+# -----------------------------------------------------------------------------

src/de1_flipflop_rtl.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity de1_flipflop is 
+port ( SW       : in  std_ulogic_vector(9 downto 0);
+       KEY      : in  std_ulogic_vector(3 downto 0); 
+       LEDG     : out std_ulogic_vector(7 downto 0);   -- green LEDs
+       LEDR     : out std_ulogic_vector(9 downto 0));  -- red LEDs
+end entity;
+
+architecture rtl of de1_flipflop is
+
+  signal rst_n,clk   : std_ulogic; 
+  signal d,q         : std_ulogic; -- for single fliplop
+  signal d0,d1,q0,q1 : std_ulogic; -- for mod4 counter
+
+begin
+    
+  --------------------------------------------------------------------
+  -- rising edge triggered flipflop with asynchronous low active reset
+  --------------------------------------------------------------------
+  q <= '0' when rst_n = '0' else d when rising_edge(clk); 
+ 
+  -----------------------------------------------------
+  -- Modulo 4 Counter
+  -----------------------------------------------------
+  -- Flipflops
+  q0 <= '0' when rst_n = '0' else d0 when rising_edge(clk);
+  q1 <= '0' when rst_n = '0' else d1 when rising_edge(clk); 
+  -- Next State Logic
+  d0 <= not q0;
+  d1 <= q0 xor q1; 
+
+  ---------------------------------------------------------
+  -- Connections to switches, leds and keys
+  ---------------------------------------------------------
+  -- Common connections for flipflop and counter
+  rst_n   <= KEY(0);         -- KEYS are 0 when pushed...
+  clk     <= KEY(1);         -- KEYS are 0 when pushed...
+  LEDG(0) <= rst_n;
+  LEDG(1) <= clk; 
+  -- Flipflop Connections
+  d       <= SW(0);
+  LEDG(2) <= q; 
+  -- Counter connections
+  LEDG(7) <= q1;
+  LEDG(6) <= q0;
+  LEDG(5) <= d1;
+  LEDG(4) <= d0; 
+  -- Other connections
+  LEDG(3) <= '0'; 
+  LEDR    <= SW;  
+
+end architecture rtl;

src/t_de1_flipflop.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t_de1_flipflop is
+end; 
+
+architecture tbench of t_de1_flipflop is
+
+  component de1_flipflop is 
+    port ( SW       : in  std_ulogic_vector(9 downto 0);
+           KEY      : in  std_ulogic_vector(3 downto 0); 
+           LEDG     : out std_ulogic_vector(7 downto 0);   -- green LEDs
+           LEDR     : out std_ulogic_vector(9 downto 0));  -- red LEDs
+  end component;
+
+  signal redleds                : std_ulogic_vector(9 downto 0);
+  signal greenleds              : std_ulogic_vector(7 downto 0);
+  signal clk, rst_n             : std_ulogic;
+  signal simstop                : boolean := false;
+  signal d                      : std_ulogic;
+
+begin
+
+  de1_flipflop_i0 : de1_flipflop
+    port map (
+      SW(0)               => d,
+      SW(9 downto 1)      => "000000000",
+      KEY(0)              => rst_n,
+      KEY(1)              => clk,
+      KEY(3 downto 2)     => "00",
+      LEDG                => greenleds, 
+      LEDR                => redleds);
+
+  rst_n <= '1', '0' after 20 ns, '1' after 40 ns;
+
+  clk_p : process
+    begin
+      clk <= '0';
+      wait for 10 ns;
+      clk <= '1';
+      wait for 10 ns;
+      if simstop then
+        wait;
+      end if;
+    end process clk_p;
+
+  -- This is the process where the switches are switched.
+  schalter : process
+  begin
+    d <= '0';
+    wait until rising_edge(rst_n);
+    wait until falling_edge(clk);
+    d <= '1';
+    wait for 40 ns;
+    d <= '0';
+    wait for 80 ns;
+    simstop <= true; 
+    wait; 
+  end process schalter;
+
+end; -- architecture