add sinewave to audio testbench

src/t_de1_audio.vhd

@@ -15,6 +15,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use ieee.math_real.all;
 
 entity t_de1_audio is
 end; 
@@ -45,6 +46,12 @@ end component;
   signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic;
 
   signal simrun : boolean := true;
+  
+  signal phase               : real := 0.0;
+  signal test_tone           : real;
+  signal test_tone_quantized : signed(15 downto 0);
+  signal bit_count           : integer range 0 to 31;
+
 
 begin
 
@@ -73,7 +80,7 @@ begin
     end if;
   end process clock_p;
 
-  simrun <= false after 1 ms; 
+  simrun <= false after 5 ms; 
 
   reset_p : process
   begin
@@ -82,7 +89,17 @@ begin
     reset_n <= '1';
     wait; 
   end process reset_p; 
+  
+  aud_adcdat <= test_tone_quantized(bit_count mod 16);
+
+  -- Test tone generator for simulating the ADC from the audio codec
+  phase               <= phase + 1.0/48.0 when rising_edge(aud_daclrck);
+  test_tone           <= sin(2*3.14*phase);
+  test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16);
+  bit_count           <= 31 when falling_edge(aud_daclrck) else
+                         0 when bit_count = 0 else
+                         bit_count - 1 when falling_edge(aud_bclk);
+
 
-  aud_adcdat <= '1';
 
 end; -- architecture