Commit 229ae03c authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

renamed ledcntsw to de1_ledcntsw

parent 9cd7500a
......@@ -2,10 +2,10 @@
# toplevel VHDL entity name
# and should match the directory name in the pnr directory
PROJECT = ledcntsw
PROJECT = de1_ledcntsw
SOURCE_FILES = \
../../src/ledcntsw_rtl.vhd \
../../src/de1_ledcntsw_rtl.vhd \
../../src/cntones_rtl.vhd
include ../makefile
......@@ -2,13 +2,13 @@ library ieee;
use ieee.std_logic_1164.all;
-- Two switchcounters count the number of active ones.
entity ledcntsw is
entity de1_ledcntsw is
port ( SW : in std_ulogic_vector(9 downto 0);
LEDG : out std_ulogic_vector(7 downto 0); -- green LEDs
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end entity ledcntsw;
end entity de1_ledcntsw;
architecture rtl of ledcntsw is
architecture rtl of de1_ledcntsw is
signal cnt0, cnt1 : std_ulogic_vector(2 downto 0);
......
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