Commit 3b3fff3a authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

added ledcomb unit with sim and syn

parent 29cd83d5
# Pin Configuration
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_M1 -to SW[8]
set_location_assignment PIN_L2 -to SW[9]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_R17 -to LEDR[9]
set_location_assignment PIN_U22 -to LEDG[0]
set_location_assignment PIN_U21 -to LEDG[1]
set_location_assignment PIN_V22 -to LEDG[2]
set_location_assignment PIN_V21 -to LEDG[3]
set_location_assignment PIN_W22 -to LEDG[4]
set_location_assignment PIN_W21 -to LEDG[5]
set_location_assignment PIN_Y22 -to LEDG[6]
set_location_assignment PIN_Y21 -to LEDG[7]
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = ledcomb
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# assign variable PROJECT with the top level project name
#
# Prerequisite:
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = ledcomb
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/ledcomb_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Combinational functions computed from switch values shown at the green leds
entity ledcomb is
port ( SW : in std_ulogic_vector(9 downto 0);
LEDG : out std_ulogic_vector(7 downto 0); -- green LEDs
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end entity ledcomb;
architecture rtl of ledcomb is
signal s0, s1 : std_ulogic;
begin
-- Show the switch state at the red leds
LEDR <= SW;
----------------------------------------------------------------------------
-- Boolean expressions forming boolean functions
----------------------------------------------------------------------------
-- Combinational functions from SW(4..0) shown at green leds
LEDG(0) <= not SW(0) and SW(1) and SW(2) and SW(3) and not SW(4);
-- Combinational functions from SW(1..0) shown at green leds
s0 <= SW(0) xor SW(1);
s1 <= SW(0) and SW(1);
LEDG(1) <= s0;
LEDG(2) <= s1;
LEDG(3) <= s0 or s1;
----------------------------------------------------------------------------
-- Truthtable direct method (if you have a truthtable...)
----------------------------------------------------------------------------
with SW(9 downto 5) select
LEDG(4) <=
'1' when "11111",
'1' when "00000",
'1' when "10101"|"01010", -- select more than one condition
'0' when others; -- last line must be others
-- This counts the number of ones on SW(9..6).
-- The result is computed as binary number.
with SW(9 downto 6) select
LEDG(7 downto 5) <=
"000" when "0000",
"001" when "0001"|"0010"|"0100"|"1000",
"010" when "0011"|"0101"|"1001"|"0110"|"1010"|"1100",
"011" when "0111"|"1011"|"1101"|"1110",
"100" when "1111",
"100" when others; -- required
-- One select value must be "others" because all possible
-- combinations must be listed and std_ulogic also has other possible values
-- than '0' and '1', e.g. 'Z'. However, these values only exist in simulation
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
-- Testbench for the first switch/led module
-- The switches are switched...
entity t_ledcomb is
end;
architecture tbench of t_ledcomb is
-- This is the component declaration
component ledcomb
port (
SW: in std_ulogic_vector(9 downto 0);
LEDG: out std_ulogic_vector(7 downto 0);
LEDR: out std_ulogic_vector(9 downto 0)
);
end component;
-- Signal declaration for the switches and the leds
signal switches, redleds : std_ulogic_vector(9 downto 0);
signal greenleds : std_ulogic_vector(7 downto 0);
begin
-- Here the device under test is instantiated
-- The ledsw circuit is connected to the signals in the testbench
ledcomb_i0 : ledcomb
port map (
SW => switches,
LEDG => greenleds,
LEDR => redleds);
-- This is the process where the switches are switched.
schalter : process
begin
wait for 1 us;
switches <= "0000000001";
wait for 3 us;
switches <= "1000000000";
wait for 2 us;
switches <= "0000000001";
wait for 5 us;
switches <= "1000000000";
wait for 4 us;
switches <= "1111111111";
wait for 1 us;
wait; -- wait forever
end process schalter;
end; -- architecture
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