added add4 and de1_add4 with sim and syn

pnr/de1_add4/de1_add4_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_J2  -to HEX0[0]
+set_location_assignment PIN_J1  -to HEX0[1]
+set_location_assignment PIN_H2  -to HEX0[2]
+set_location_assignment PIN_H1  -to HEX0[3]
+set_location_assignment PIN_F2  -to HEX0[4]
+set_location_assignment PIN_F1  -to HEX0[5]
+set_location_assignment PIN_E2  -to HEX0[6]
+set_location_assignment PIN_E1  -to HEX1[0]
+set_location_assignment PIN_H6  -to HEX1[1]
+set_location_assignment PIN_H5  -to HEX1[2]
+set_location_assignment PIN_H4  -to HEX1[3]
+set_location_assignment PIN_G3  -to HEX1[4]
+set_location_assignment PIN_D2  -to HEX1[5]
+set_location_assignment PIN_D1  -to HEX1[6]
+set_location_assignment PIN_G5  -to HEX2[0]
+set_location_assignment PIN_G6  -to HEX2[1]
+set_location_assignment PIN_C2  -to HEX2[2]
+set_location_assignment PIN_C1  -to HEX2[3]
+set_location_assignment PIN_E3  -to HEX2[4]
+set_location_assignment PIN_E4  -to HEX2[5]
+set_location_assignment PIN_D3  -to HEX2[6]
+
+
+

pnr/de1_add4/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = de1_add4
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

sim/add4/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = add4
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+
+

sim/add4/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/add4_rtl.vhd 
+
+# do not delete this line
+# -----------------------------------------------------------------------------

sim/de1_add4/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = de1_add4
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+
+

sim/de1_add4/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/de1_add4_rtl.vhd \
+../../src/add4_rtl.vhd  \
+../../src/bin2seg_rtl.vhd 
+
+# do not delete this line
+# -----------------------------------------------------------------------------

src/add4_rtl.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Add two 4 Bit numbers
+entity add4 is 
+port ( a_i   : in      std_ulogic_vector(3 downto 0);
+       b_i   : in      std_ulogic_vector(3 downto 0);
+       y_o   : out     std_ulogic_vector(3 downto 0));    
+end entity;
+
+architecture rtl of add4 is 
+
+begin
+  
+  y_o <= std_ulogic_vector(unsigned(a_i) + unsigned(b_i)); 
+ 
+end architecture rtl;

src/de1_add4_rtl.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity de1_add4 is 
+port ( SW   : in      std_ulogic_vector(9 downto 0);
+       HEX0 : out     std_ulogic_vector(6 downto 0);
+       HEX1 : out     std_ulogic_vector(6 downto 0);
+       HEX2 : out     std_ulogic_vector(6 downto 0);
+       LEDG : out     std_ulogic_vector(7 downto 0);
+       LEDR : out     std_ulogic_vector(9 downto 0));
+end entity;
+
+architecture rtl of de1_add4 is
+  
+  component bin2seg is 
+  port ( bin_i   : in      std_ulogic_vector(3 downto 0);
+         seg_o   : out     std_ulogic_vector(6 downto 0));  
+  end component;
+
+  component add4 is 
+  port ( a_i   : in      std_ulogic_vector(3 downto 0);
+         b_i   : in      std_ulogic_vector(3 downto 0);
+         y_o   : out     std_ulogic_vector(3 downto 0));    
+  end component;
+
+begin
+  
+end architecture rtl;

src/t_add4.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t_add4 is
+end; 
+
+architecture tbench of t_add4 is
+
+  component add4 is 
+  port ( a_i   : in      std_ulogic_vector(3 downto 0);
+         b_i   : in      std_ulogic_vector(3 downto 0);
+         y_o   : out     std_ulogic_vector(3 downto 0));    
+  end component;
+
+  signal a,b,y : std_ulogic_vector(3 downto 0);
+
+begin
+
+  -- Here the device under test is instantiated
+  add4_i0 : add4
+    port map (
+      a_i => a,
+      b_i => b,
+      y_o => y);
+
+  -- In this process the values for the summands a and b are set
+  schalter : process
+  begin
+    a <= "0000";
+    b <= "0000"; 
+    wait for 1 us; 
+    a <= "0001";
+    b <= "1000"; 
+    wait for 1 us;
+    a <= "0011";
+    b <= "0101"; 
+    wait for 1 us;
+    a <= "0111";
+    b <= "0011"; 
+    wait for 1 us;
+    a <= "1001";
+    b <= "0011"; 
+    wait for 1 us;
+    a <= "0101";
+    b <= "0100"; 
+    wait for 1 us;
+    a <= "1111";
+    b <= "1111"; 
+    wait for 1 us; 
+    wait;                               -- wait forever
+  end process schalter;
+
+end; -- architecture

src/t_de1_add4.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t_de1_add4 is
+end; 
+
+architecture tbench of t_de1_add4 is
+
+-- This is the component declaration 
+  component de1_add4 is 
+  port ( SW   : in      std_ulogic_vector(9 downto 0);
+         HEX0 : out     std_ulogic_vector(6 downto 0);
+         HEX1 : out     std_ulogic_vector(6 downto 0);
+         HEX2 : out     std_ulogic_vector(6 downto 0);
+         LEDG : out     std_ulogic_vector(7 downto 0);
+         LEDR : out     std_ulogic_vector(9 downto 0));  
+  end component;
+
+  signal switches, redleds : std_ulogic_vector(9 downto 0);
+  signal greenleds         : std_ulogic_vector(7 downto 0);  
+  signal hex0,hex1,hex2    : std_ulogic_vector(6 downto 0); 
+
+begin
+
+  de1_add4_i0 : de1_add4
+    port map (
+      SW                  => switches,
+      HEX0                => hex0,
+      HEX1                => hex1,
+      HEX2                => hex2,
+      LEDG                => greenleds, 
+      LEDR                => redleds);
+
+  -- This is the process where the switches are switched.
+  schalter : process
+  begin
+    wait for 1 us; 
+    switches <= "0000000001";
+    wait for 1 us;
+    switches <= "1000000000";
+    wait for 1 us; 
+    switches <= "0011000111";
+    wait for 1 us;
+    switches <= "1001000011"; 
+    wait for 1 us;
+    switches <= "1111111111";
+    wait for 1 us; 
+    wait;                               -- wait forever
+  end process schalter;
+
+end; -- architecture