Commit 40fad16a authored by Johann Faerber's avatar Johann Faerber
Browse files

added missing files of binto7segment

parent bd12eab6
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
# ----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : de1_binto7segment
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: test the module binto7segment on a DE1 prototype board
-- connecting device under test (DUT) binto7segment
-- to input/output signals of the DE1 prototype board
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY de1_binto7segment IS
PORT (
SW : IN std_ulogic_vector(3 DOWNTO 0); -- Toggle Switch[3:0]
LEDR : OUT std_ulogic_vector(3 DOWNTO 0); -- LED Red[3:0]
HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0
);
END de1_binto7segment;
ARCHITECTURE structure OF de1_binto7segment IS
COMPONENT binto7segment
PORT (
bin_i : IN std_ulogic_vector(3 DOWNTO 0);
segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
END COMPONENT;
BEGIN
-- connecting device under test with peripheral elements
DUT : binto7segment
PORT MAP (
bin_i => SW,
segments_o => HEX0);
-- connect switches to red LEDs
LEDR <= SW;
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : binto7segment_stimuli
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: stimuli for verification of binary-to-7-segment decoder
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY binto7segment_stimuli IS
PORT (
stimuli_o : OUT std_ulogic_vector(3 DOWNTO 0)
);
END binto7segment_stimuli;
ARCHITECTURE stimuli OF binto7segment_stimuli IS
-- definition of a clock period
CONSTANT period : time := 10 ns;
BEGIN
stimuli_p : PROCESS
BEGIN
stimuli_o <= "0000";
WAIT FOR period;
stimuli_o <= "0001";
WAIT FOR period;
stimuli_o <= "0010";
WAIT FOR period;
stimuli_o <= "0011";
WAIT FOR period;
stimuli_o <= "0100";
WAIT FOR period;
stimuli_o <= "0101";
WAIT FOR period;
stimuli_o <= "0110";
WAIT FOR period;
stimuli_o <= "0111";
WAIT FOR period;
stimuli_o <= "1000";
WAIT FOR period;
stimuli_o <= "1001";
WAIT FOR period;
stimuli_o <= "1010";
WAIT FOR period;
stimuli_o <= "1011";
WAIT FOR period;
stimuli_o <= "1100";
WAIT FOR period;
stimuli_o <= "1101";
WAIT FOR period;
stimuli_o <= "1110";
WAIT FOR period;
stimuli_o <= "1111";
WAIT FOR period;
WAIT;
END PROCESS;
END stimuli;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/binto7segment_truthtable.vhd \
-------------------------------------------------------------------------------
-- Module : t_binto7segment
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Testbench for design "binto7segment"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_binto7segment IS
END t_binto7segment;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_binto7segment IS
COMPONENT binto7segment_stimuli
PORT (
stimuli_o : OUT std_ulogic_vector(3 DOWNTO 0));
END COMPONENT;
COMPONENT binto7segment
PORT (
bin_i : IN std_ulogic_vector(3 DOWNTO 0);
segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
END COMPONENT;
-- stimuli generator ports
SIGNAL stimuli_o : std_ulogic_vector(3 DOWNTO 0);
-- component ports
-- SIGNAL bin_i : std_ulogic_vector(3 DOWNTO 0);
SIGNAL segments_o : std_ulogic_vector(6 DOWNTO 0);
BEGIN -- tbench
-- component instantiation
MUV : binto7segment
PORT MAP (
bin_i => stimuli_o,
segments_o => segments_o);
stimuli : binto7segment_stimuli
PORT MAP (
stimuli_o => stimuli_o);
END tbench;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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