Commit 4591dd18 authored by Johann Faerber's avatar Johann Faerber
Browse files

- again, trying to complete scripts/de1_pin_assignments_minimumio.tcl

- added file scripts/design_project_directory_structure.txt
- added credentials for Friedrich Beckmann in header blocks
- added appropriate comments to understand makefiles
- moved testbenches and test environment source files to src dir
parent e86cf414
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: - mandatory design directory structure (see end of file)
# - scripts/quartus_project_settings.tcl
# - scripts/de1_$(PROJECT)_pins.tcl
#
# - modify and copy it to pnr/de1_(PROJECT)/makefile
# - specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = add1
PROJECT = de1_$(SIM_PROJECT_NAME)
......@@ -26,7 +28,7 @@ include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./$(PROJECT)_structure.vhd
../../src/$(PROJECT)_structure.vhd
include ../makefile
......
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: - mandatory design directory structure (see end of file)
# - scripts/quartus_project_settings.tcl
# - scripts/de1_$(PROJECT)_pins.tcl
#
# - modify and copy it to pnr/de1_(PROJECT)/makefile
# - specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = binto7segment
PROJECT = de1_$(SIM_PROJECT_NAME)
......@@ -26,7 +28,7 @@ include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./$(PROJECT)_structure.vhd
../../src/$(PROJECT)_structure.vhd
include ../makefile
......
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: - mandatory design directory structure (see end of file)
# - scripts/quartus_project_settings.tcl
# - scripts/de1_$(PROJECT)_pins.tcl
#
# - modify and copy it to pnr/de1_(PROJECT)/makefile
# - specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = mux2to1
PROJECT = de1_$(SIM_PROJECT_NAME)
......@@ -26,8 +28,42 @@ include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./$(PROJECT)_structure.vhd
../../src/$(PROJECT)_structure.vhd
include ../makefile
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure shown at
## the end of this file.
## ----------------------------------------------------------------------------
###################################################################
......@@ -50,46 +52,30 @@ quartus: flowsummary.log
## |
## +---src
## | and2gate_equation.vhd
## | de1_mux2to1_structure.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## |
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | +---de1_mux2to1
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## | de1_mux2to1.qpf
## | de1_mux2to1.qpf
## |
## +---scripts
## | quartus_project_settings.tcl
## | makefile.quartus_template
## | makefile.modelsim_template
## | de1_mux2to1_pins.tcl
## | modelsim_project_settings.tcl
## | modelsim.ini
## | de1_pin_assignments_minimumio.csv
## | de1_pin_assignments_minimumio.tcl
## |
## \---sim
## +---mux2to1
## makefile
## mux2to1.mpf
## modelsim.ini
##
## ----------------------------------------------------------------------------
## Modifications: makefile template from Altera Quartus scripting modified:
## --------------
## - added help target
## - removed target for timing analysis
## - added target project for initial creation of a quartus project
## - modified target all to compile
## - modified target clean to remove quartus project files *.qpf *.qfs
## - added target prog to configure a programmable device
## - added target quartus to start quartus graphical user interface
## ----------------------------------------------------------------------------
## Revisions:
## ----------
## $Id:$
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
......@@ -36,6 +36,13 @@ set_location_assignment PIN_W22 -to LEDG[4]
set_location_assignment PIN_W21 -to LEDG[5]
set_location_assignment PIN_Y22 -to LEDG[6]
set_location_assignment PIN_Y21 -to LEDG[7]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
set_location_assignment PIN_E1 -to HEX1[0]
set_location_assignment PIN_H6 -to HEX1[1]
set_location_assignment PIN_H5 -to HEX1[2]
......
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, F. Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: create a quartus project with default settings for device,
......@@ -48,7 +48,7 @@ if {[string equal "" $arg(projectname)]} {
# Design files
#set_global_assignment -name VHDL_FILE ../src/e_cntdnmodm.vhd
#set_global_assignment -name VHDL_FILE ../src/a_cntdnmodm_rtl.vhd
source quartus_vhdl_source_files.tcl
source quartus_vhdl_source_files.tcl
# ----------------------------------------------------------------------------
# Pin Assignments
......@@ -56,17 +56,17 @@ if {[string equal "" $arg(projectname)]} {
# set_location_assignment PIN_L1 -to CLOCK_50
source $arg(projectname)_pins.tcl
# -----------------------
# Run the synthesis
# -----------------------
load_package flow
# -----------------------
# Run the synthesis
# -----------------------
load_package flow
execute_flow -compile
execute_flow -compile
# Write Reports
load_package report
load_report $arg(projectname)
write_report_panel -file flowsummary.log "Flow Summary"
# Write Reports
load_package report
load_report $arg(projectname)
write_report_panel -file flowsummary.log "Flow Summary"
# ----------------------------------------------------------------------------
# Close project
......
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: mandatory design directory structure (see end of file)
# assign variable PROJECT with the top level project name
#
# - modify and copy it to sim/(PROJECT)/makefile
# - Specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = add1
......@@ -23,7 +25,7 @@ include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./t_$(PROJECT).vhd
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
......
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: mandatory design directory structure (see end of file)
# assign variable PROJECT with the top level project name
#
# - modify and copy it to sim/(PROJECT)/makefile
# - Specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = binto7segment
......@@ -23,8 +25,8 @@ include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./binto7segment_stimuli.vhd \
./t_$(PROJECT).vhd
../../src/binto7segment_stimuli.vhd \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
......
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author(s) : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure shown at
## the end of this file.
## ----------------------------------------------------------------------------
###################################################################
# Main Targets
#
......@@ -26,16 +26,11 @@ mproject : $(PROJECT).mpf
$(PROJECT).mpf : $(SOURCE_FILES)
# create modelsim project
# vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); quit -f"
rm -rf ./modelsim_sources.tcl
for source_file in $(SOURCE_FILES); do \
echo project addfile $$source_file >> modelsim_sources.tcl; \
done
vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f"
# assign VHDL design files
# for source_file in $(SOURCE_FILES); do \
# vsim -c -do "project open $(PROJECT); project addfile $$source_file; quit -f" ; \
# done
compile: ./work/_vmake
......@@ -60,44 +55,30 @@ clean:
## |
## +---src
## | and2gate_equation.vhd
## | de1_mux2to1_structure.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## |
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | +---de1_mux2to1
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## | de1_mux2to1.qpf
## | de1_mux2to1.qpf
## |
## +---scripts
## | quartus_project_settings.tcl
## | makefile.quartus_template
## | makefile.modelsim_template
## | de1_mux2to1_pins.tcl
## | modelsim_project_settings.tcl
## | modelsim.ini
## | de1_pin_assignments_minimumio.csv
## | de1_pin_assignments_minimumio.tcl
## |
## \---sim
## +---mux2to1
## makefile
## mux2to1.mpf
## modelsim.ini
##
## ----------------------------------------------------------------------------
## Modifications: makefile template from Altera Quartus scripting modified:
## --------------
## - added help target
## - make project to create a new modelsim project
## - make modelsim to start modelsim with graphical user interface
## - make sim to start modelsim gui with the top testbench of the project
## - make compile to compile all VHDL sources in batch mode
## ----------------------------------------------------------------------------
## Revisions:
## ----------
## $Id:$
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: mandatory design directory structure (see end of file)
# assign variable PROJECT with the top level project name
#
# - modify and copy it to sim/(PROJECT)/makefile
# - Specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = mux2to1
......@@ -23,7 +25,43 @@ include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./t_$(PROJECT).vhd
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
......