Commit 5b70e475 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

added ledcntsw module with syn and sim

parent 54869bf9
# Pin Configuration
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_M1 -to SW[8]
set_location_assignment PIN_L2 -to SW[9]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_R17 -to LEDR[9]
set_location_assignment PIN_U22 -to LEDG[0]
set_location_assignment PIN_U21 -to LEDG[1]
set_location_assignment PIN_V22 -to LEDG[2]
set_location_assignment PIN_V21 -to LEDG[3]
set_location_assignment PIN_W22 -to LEDG[4]
set_location_assignment PIN_W21 -to LEDG[5]
set_location_assignment PIN_Y22 -to LEDG[6]
set_location_assignment PIN_Y21 -to LEDG[7]
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = ledcntsw
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# assign variable PROJECT with the top level project name
#
# Prerequisite:
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = cntones
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/cntones_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# assign variable PROJECT with the top level project name
#
# Prerequisite:
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = ledcntsw
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/ledcntsw_rtl.vhd \
../../src/cntones_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Count the number of '1' in the switches_i signal
-- Example: "1011" should give "011" at cnt_o as there are 3 ones active.
entity cntones is
port ( switches_i : in std_ulogic_vector(3 downto 0);
cnt_o : out std_ulogic_vector(2 downto 0));
end entity cntones;
architecture rtl of cntones is
begin
-- This counts the number of ones in switches_i.
-- The result is computed as binary number.
with switches_i select
cnt_o <=
"000" when "0000",
"001" when "0001"|"0010"|"0100"|"1000",
"010" when "0011"|"0101"|"1001"|"0110"|"1010"|"1100",
"011" when "0111"|"1011"|"1101"|"1110",
"100" when "1111",
"100" when others; -- required
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
-- Two switchcounters count the number of active ones.
entity ledcntsw is
port ( SW : in std_ulogic_vector(9 downto 0);
LEDG : out std_ulogic_vector(7 downto 0); -- green LEDs
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end entity ledcntsw;
architecture rtl of ledcntsw is
signal cnt0, cnt1 : std_ulogic_vector(2 downto 0);
-- Component declaration for the countones module
component cntones is
port ( switches_i : in std_ulogic_vector(3 downto 0);
cnt_o : out std_ulogic_vector(2 downto 0));
end component cntones;
begin
-- Show the switch state at the red leds
LEDR <= SW;
----------------------------------------------------------------------------
-- Instantiate the cntones module two times with different input and output signals
----------------------------------------------------------------------------
cntones_i0 : cntones
port map (
switches_i => SW(3 downto 0),
cnt_o => LEDG(2 downto 0));
cntones_i1 : cntones
port map (
switches_i => SW(9 downto 6),
cnt_o => LEDG(7 downto 5));
-- Switch off the unused green leds
LEDG(4 downto 3) <= "00";
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity t_cntones is
end;
architecture tbench of t_cntones is
component cntones is
port ( switches_i : in std_ulogic_vector(3 downto 0);
cnt_o : out std_ulogic_vector(2 downto 0));
end component cntones;
signal switches : std_ulogic_vector(3 downto 0);
signal cnt : std_ulogic_vector(2 downto 0);
begin
-- Here the device under test is instantiated
cntones_i0 : cntones
port map (
switches_i => switches,
cnt_o => cnt);
-- This is the process where the switches are switched.
schalter : process
begin
wait for 1 us;
switches <= "0000";
wait for 3 us;
switches <= "0001";
wait for 2 us;
switches <= "1001";
wait for 5 us;
switches <= "1011";
wait for 4 us;
switches <= "1111";
wait for 1 us;
wait; -- wait forever
end process schalter;
end; -- architecture
library ieee;
use ieee.std_logic_1164.all;
entity t_ledcntsw is
end;
architecture tbench of t_ledcntsw is
-- This is the component declaration
component ledcntsw
port (
SW: in std_ulogic_vector(9 downto 0);
LEDG: out std_ulogic_vector(7 downto 0);
LEDR: out std_ulogic_vector(9 downto 0)
);
end component;
-- Signal declaration for the switches and the leds
signal switches, redleds : std_ulogic_vector(9 downto 0);
signal greenleds : std_ulogic_vector(7 downto 0);
begin
-- Here the device under test is instantiated
-- The ledsw circuit is connected to the signals in the testbench
ledcntsw_i0 : ledcntsw
port map (
SW => switches,
LEDG => greenleds,
LEDR => redleds);
-- This is the process where the switches are switched.
schalter : process
begin
wait for 1 us;
switches <= "0000000001";
wait for 3 us;
switches <= "1000000000";
wait for 2 us;
switches <= "0000000001";
wait for 5 us;
switches <= "1000000000";
wait for 4 us;
switches <= "1111111111";
wait for 1 us;
wait; -- wait forever
end process schalter;
end; -- architecture
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