add de1_dac

pnr/de1_dac/de1_dac_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L1  -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY0
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+# DAC Pins on GPIO Header
+set_location_assignment  PIN_C19  -to DAC_CLK_A
+set_location_assignment  PIN_D19  -to DAC_CLK_B
+set_location_assignment  PIN_C18  -to DAC_DA[0]
+set_location_assignment  PIN_F15  -to DAC_DA[10]
+set_location_assignment  PIN_E14  -to DAC_DA[11]
+set_location_assignment  PIN_G15  -to DAC_DA[12]
+set_location_assignment  PIN_H13  -to DAC_DA[13]
+set_location_assignment  PIN_D16  -to DAC_DA[1]
+set_location_assignment  PIN_C17  -to DAC_DA[2]
+set_location_assignment  PIN_D15  -to DAC_DA[3]
+set_location_assignment  PIN_D14  -to DAC_DA[4]
+set_location_assignment  PIN_F13  -to DAC_DA[5]
+set_location_assignment  PIN_C14  -to DAC_DA[6]
+set_location_assignment  PIN_F12  -to DAC_DA[7]
+set_location_assignment  PIN_G16  -to DAC_DA[8]
+set_location_assignment  PIN_E15  -to DAC_DA[9]
+set_location_assignment  PIN_P15  -to DAC_DB[0]
+set_location_assignment  PIN_G20  -to DAC_DB[10]
+set_location_assignment  PIN_E19  -to DAC_DB[11]
+set_location_assignment  PIN_F20  -to DAC_DB[12]
+set_location_assignment  PIN_D20  -to DAC_DB[13]
+set_location_assignment  PIN_N22  -to DAC_DB[1]
+set_location_assignment  PIN_N15  -to DAC_DB[2]
+set_location_assignment  PIN_N21  -to DAC_DB[3]
+set_location_assignment  PIN_J15  -to DAC_DB[4]
+set_location_assignment  PIN_G17  -to DAC_DB[5]
+set_location_assignment  PIN_H18  -to DAC_DB[6]
+set_location_assignment  PIN_H17  -to DAC_DB[7]
+set_location_assignment  PIN_G18  -to DAC_DB[8]
+set_location_assignment  PIN_E18  -to DAC_DB[9]
+set_location_assignment  PIN_P18  -to DAC_MODE
+set_location_assignment  PIN_C20  -to DAC_WRT_A
+set_location_assignment  PIN_P17  -to DAC_WRT_B
+set_location_assignment  PIN_C21  -to ADC_CLK_A
+set_location_assignment  PIN_D21  -to ADC_CLK_B
+set_location_assignment  PIN_L18  -to ADC_OEB_A
+set_location_assignment  PIN_K20  -to ADC_OEB_B
+set_location_assignment  PIN_J18  -to POWER_ON

pnr/de1_dac/makefile

+
+SIM_PROJECT_NAME = de1_dac
+PROJECT = $(SIM_PROJECT_NAME)
+
+SOURCE_FILES = ../../src/de1_dac_rtl.vhd
+
+include ../makefile
+
+

src/de1_dac_rtl.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity de1_dac is 
+  port ( CLOCK_50 : in  std_ulogic;         
+         SW       : in  std_ulogic_vector(9 downto 0); 
+         KEY0     : in  std_ulogic;
+         DAC_MODE : out std_ulogic;    --1=dual port, 0=interleaved
+         DAC_WRT_A : out std_ulogic;
+         DAC_WRT_B : out std_ulogic;
+         DAC_CLK_A : out std_ulogic;  -- PLL_OUT_DAC0 in User Manual
+         DAC_CLK_B : out std_ulogic;  -- PLL_OUT_DAC1 in User Manual
+         DAC_DA   : out std_ulogic_vector(13 downto 0);
+         DAC_DB   : out std_ulogic_vector(13 downto 0);
+         ADC_CLK_A : out std_ulogic;
+         ADC_CLK_B : out std_ulogic;
+         POWER_ON  : out std_ulogic;
+         ADC_OEB_A : out std_ulogic;
+         ADC_OEB_B : out std_ulogic;
+         LEDR     : out std_ulogic_vector(9 downto 0));  -- red LEDs
+end entity;
+
+architecture rtl of de1_dac is
+
+  signal clk,rst_n : std_ulogic;
+  signal cnt : unsigned(13 downto 0);
+  signal phase_inc : unsigned(9 downto 0);
+  signal dac_a_reg, dac_a_next, dac_b_reg : unsigned(13 downto 0);
+  
+begin
+
+  clk <= CLOCK_50;
+  rst_n <= KEY0;
+  LEDR <= SW;
+  
+  DAC_MODE  <= '1'; --dual port
+  DAC_CLK_A <= clk;
+  DAC_CLK_B <= clk;
+  DAC_WRT_A <= clk;
+  DAC_WRT_B <= clk;
+
+  phase_inc <= unsigned(SW);
+
+  cnt <= (others => '0') when rst_n = '0' else cnt+phase_inc when rising_edge(clk);
+
+  dac_a_next <= (others => '1') when cnt = 0 else (others => '0');
+  dac_a_reg <= (others => '0') when rst_n = '0' else dac_a_next when falling_edge(clk);
+  dac_b_reg <= (others => '0') when rst_n = '0' else cnt when falling_edge(clk); 
+  DAC_DA <= std_ulogic_vector(dac_a_reg);
+  DAC_DB <= std_ulogic_vector(dac_b_reg);
+
+  -- ADC Section - switch off everything
+  ADC_CLK_A <= '0';
+  ADC_CLK_B <= '0';
+  ADC_OEB_A <= '1';
+  ADC_OEB_B <= '1';
+  POWER_ON  <= '1';
+
+end architecture rtl;