Commit 6b86ff8a authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

make based synthesis

parent b3188e79
# Pin Configuration
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_M1 -to SW[8]
set_location_assignment PIN_L2 -to SW[9]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_R17 -to LEDR[9]
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = ledsw
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure shown at
## the end of this file.
## ----------------------------------------------------------------------------
###################################################################
# Main Targets
#
###################################################################
help:
@echo '"make" does intentionally nothing. Type:'
@echo ' "make compile" synthesize the design'
@echo ' "make prog" to configure programmable device'
@echo ' "make quartus" to start quartus graphical user interface'
@echo ' "make clean" to remove all generated files'
compile: flowsummary.log
flowsummary.log: $(SOURCE_FILES)
# assign VHDL design files
rm -rf quartus_vhdl_source_files.tcl
for source_file in $(SOURCE_FILES); do \
echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \
done
# create and compile quartus project
quartus_sh -t ../../scripts/quartus_project_settings.tcl -projectname $(PROJECT) -family $(FAMILY) -device $(DEVICE)
clean:
rm -rf *.rpt *.chg *.log quartus_vhdl_source_files.tcl *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary $(PROJECT).*
prog: flowsummary.log
quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).sof"
quartus: flowsummary.log
# create quartus project
quartus $(PROJECT).qpf &
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure shown at
## the end of this file.
## ----------------------------------------------------------------------------
###################################################################
# Main Targets
#
###################################################################
help:
@echo '"make" does intentionally nothing. Type:'
@echo ' "make qproject" to create quartus project only'
@echo ' "make compile" to synthesize the design'
@echo ' "make prog" to configure programmable device'
@echo ' "make quartus" to start quartus graphical user interface'
@echo ' "make clean" to remove all generated files'
qproject: $(PROJECT).qpf
$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl
# assign VHDL design files
rm -rf quartus_vhdl_source_files.tcl
for source_file in $(SOURCE_FILES); do \
echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \
done
# just create a quartus project
quartus_sh -t ../../scripts/create_quartus_project_settings.tcl -projectname $(PROJECT)
compile: flowsummary.log
flowsummary.log: $(PROJECT).qpf ../../scripts/quartus_project_flow.tcl
quartus_sh -t ../../scripts/quartus_project_flow.tcl -projectname $(PROJECT)
prog: flowsummary.log
quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).sof"
quartus: $(PROJECT).qpf
# start quartus gui
quartus $(PROJECT).qpf &
clean:
rm -rf *~ *.rpt *.chg *.log quartus_vhdl_source_files.tcl *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary $(PROJECT).*
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : create_quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## Author : Johann Faerber, F. Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: create a quartus project with default settings for device,
## unused pins, ...
## expects project name as command line parameter
## It expects one file containing the vhdl source files and
## one file containing the pin constraints.
## Start with
## quartus_sh -t create_quartus_project_settings.tcl -projectname de1_mux2to1
package require cmdline
# Load Quartus II Tcl Project package
package require ::quartus::project
# ----------------------------------------------------------------------------
# Declare command line parameters
# ----------------------------------------------------------------------------
set parameters {
{projectname.arg "" "Project Name"}
}
array set arg [::cmdline::getoptions argv $parameters]
# ----------------------------------------------------------------------------
# Verify required paramters
# ----------------------------------------------------------------------------
set requiredParameters {projectname}
foreach parameter $requiredParameters {
if {$arg($parameter) == ""} {
puts stderr "Missing required parameter: -$parameter"
exit 1
}
}
# ----------------------------------------------------------------------------
# Create project
# ----------------------------------------------------------------------------
project_new $arg(projectname) -overwrite
# ----------------------------------------------------------------------------
# Assign family, device, and top-level file
# ----------------------------------------------------------------------------
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
# ----------------------------------------------------------------------------
# Default settings
# ----------------------------------------------------------------------------
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
# ----------------------------------------------------------------------------
# Design files
# ----------------------------------------------------------------------------
#set_global_assignment -name VHDL_FILE ../src/e_cntdnmodm.vhd
#set_global_assignment -name VHDL_FILE ../src/a_cntdnmodm_rtl.vhd
# The following file is generated by the make process and contains
# the vhdl files which belong to the project
source quartus_vhdl_source_files.tcl
# ----------------------------------------------------------------------------
# Pin Assignments
# ----------------------------------------------------------------------------
# set_location_assignment PIN_L1 -to CLOCK_50
source $arg(projectname)_pins.tcl
# ----------------------------------------------------------------------------
# Close project
# ----------------------------------------------------------------------------
project_close
## ----------------------------------------------------------------------------
## Script : quartus_project_flow.tcl
## ----------------------------------------------------------------------------
## Author : Johann Faerber, F. Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: executes process steps in a quartus project
## depending on the parameter process
## expects project name as command line parameter
## e.g.
## quartus_sh -t quartus_project_flow.tcl -projectname de1_mux2to1
## -process compile
## ----------------------------------------------------------------------------
## Revisions : see end of file
## ----------------------------------------------------------------------------
package require cmdline
# Load Quartus II Tcl Project package
package require ::quartus::project
# ----------------------------------------------------------------------------
# Declare command line parameters
# ----------------------------------------------------------------------------
set parameters {
{projectname.arg "" "Project Name"}
}
array set arg [::cmdline::getoptions argv $parameters]
# ----------------------------------------------------------------------------
# Verify required paramters
# ----------------------------------------------------------------------------
set requiredParameters {projectname}
foreach parameter $requiredParameters {
if {$arg($parameter) == ""} {
puts stderr "Missing required parameter: -$parameter"
exit 1
}
}
# ----------------------------------------------------------------------------
# Check, if project exists
# ----------------------------------------------------------------------------
if { ![project_exists $arg(projectname)] } {
post_message -type error "Project $arg(projectname) does not exist"
exit
}
# ----------------------------------------------------------------------------
# Open project
# ----------------------------------------------------------------------------
project_open $arg(projectname)
# ----------------------------------------------------------------------------
# Run specified design flow by parameter -process
# ----------------------------------------------------------------------------
load_package flow
execute_flow -compile
# ----------------------------------------------------------------------------
# Write Reports
# ----------------------------------------------------------------------------
load_package report
load_report $arg(projectname)
write_report_panel -file flowsummary.log "Flow Summary"
# ----------------------------------------------------------------------------
# Close project
# ----------------------------------------------------------------------------
project_close
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/ledsw_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
\ No newline at end of file
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