Skip to content
GitLab
Menu
Projects
Groups
Snippets
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
Open sidebar
Friedrich Beckmann
digitaltechnikpraktikum
Commits
6c8ec948
Commit
6c8ec948
authored
Mar 27, 2014
by
Friedrich Beckmann
Browse files
removed files which are now digi_lab_problems
parent
950e33db
Changes
43
Show whitespace changes
Inline
Side-by-side
pnr/de1_add1/de1_add1_pins.tcl
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW
[
0
]
set_location_assignment PIN_L21 -to SW
[
1
]
set_location_assignment PIN_M22 -to SW
[
2
]
set_location_assignment PIN_R20 -to LEDR
[
0
]
set_location_assignment PIN_R19 -to LEDR
[
1
]
# ----------------------------------------------------------------------------
pnr/de1_add1/makefile
deleted
100644 → 0
View file @
950e33db
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME
=
add1
PROJECT
=
de1_
$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
# Here the VHDL files for synthesis are defined.
include
../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/
$(PROJECT)
_structure.vhd
include
../makefile
pnr/de1_add4/de1_add4_pins.tcl
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW
[
0
]
set_location_assignment PIN_L21 -to SW
[
1
]
set_location_assignment PIN_M22 -to SW
[
2
]
set_location_assignment PIN_V12 -to SW
[
3
]
set_location_assignment PIN_W12 -to SW
[
4
]
set_location_assignment PIN_U12 -to SW
[
5
]
set_location_assignment PIN_U11 -to SW
[
6
]
set_location_assignment PIN_M2 -to SW
[
7
]
set_location_assignment PIN_M1 -to SW
[
8
]
set_location_assignment PIN_R20 -to LEDR
[
0
]
set_location_assignment PIN_R19 -to LEDR
[
1
]
set_location_assignment PIN_U19 -to LEDR
[
2
]
set_location_assignment PIN_Y19 -to LEDR
[
3
]
set_location_assignment PIN_T18 -to LEDR
[
4
]
set_location_assignment PIN_V19 -to LEDR
[
5
]
set_location_assignment PIN_Y18 -to LEDR
[
6
]
set_location_assignment PIN_U18 -to LEDR
[
7
]
set_location_assignment PIN_R18 -to LEDR
[
8
]
set_location_assignment PIN_U22 -to LEDG
[
0
]
set_location_assignment PIN_U21 -to LEDG
[
1
]
set_location_assignment PIN_V22 -to LEDG
[
2
]
set_location_assignment PIN_V21 -to LEDG
[
3
]
set_location_assignment PIN_W22 -to LEDG
[
4
]
set_location_assignment PIN_J2 -to HEX0
[
0
]
set_location_assignment PIN_J1 -to HEX0
[
1
]
set_location_assignment PIN_H2 -to HEX0
[
2
]
set_location_assignment PIN_H1 -to HEX0
[
3
]
set_location_assignment PIN_F2 -to HEX0
[
4
]
set_location_assignment PIN_F1 -to HEX0
[
5
]
set_location_assignment PIN_E2 -to HEX0
[
6
]
set_location_assignment PIN_E1 -to HEX1
[
0
]
set_location_assignment PIN_H6 -to HEX1
[
1
]
set_location_assignment PIN_H5 -to HEX1
[
2
]
set_location_assignment PIN_H4 -to HEX1
[
3
]
set_location_assignment PIN_G3 -to HEX1
[
4
]
set_location_assignment PIN_D2 -to HEX1
[
5
]
set_location_assignment PIN_D1 -to HEX1
[
6
]
set_location_assignment PIN_G5 -to HEX2
[
0
]
set_location_assignment PIN_G6 -to HEX2
[
1
]
set_location_assignment PIN_C2 -to HEX2
[
2
]
set_location_assignment PIN_C1 -to HEX2
[
3
]
set_location_assignment PIN_E3 -to HEX2
[
4
]
set_location_assignment PIN_E4 -to HEX2
[
5
]
set_location_assignment PIN_D3 -to HEX2
[
6
]
set_location_assignment PIN_H12 -to GPO_1
[
0
]
set_location_assignment PIN_H13 -to GPO_1
[
1
]
set_location_assignment PIN_L1 -to CLOCK_50
# ----------------------------------------------------------------------------
pnr/de1_add4/makefile
deleted
100644 → 0
View file @
950e33db
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME
=
add4
PROJECT
=
de1_
$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
# Here the VHDL files for synthesis are defined.
include
../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/binto7segment_truthtable.vhd
\
../../src/
$(PROJECT)
_structure.vhd
include
../makefile
pnr/de1_binto7segment/de1_binto7segment.qpf
deleted
100644 → 0
View file @
950e33db
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:47:05 September 17, 2013
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "16:47:05 September 17, 2013"
# Revisions
PROJECT_REVISION = "de1_binto7segment"
pnr/de1_binto7segment/de1_binto7segment.qsf
deleted
100644 → 0
View file @
950e33db
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 16:47:05 September 17, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# de1_binto7segment_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20F484C7
set_global_assignment -name TOP_LEVEL_ENTITY de1_binto7segment
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:47:05 SEPTEMBER 17, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_FILE ../../src/binto7segment_truthtable.vhd
set_global_assignment -name VHDL_FILE ../../src/de1_binto7segment_structure.vhd
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
\ No newline at end of file
pnr/de1_binto7segment/de1_binto7segment_pins.qsf
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
# ----------------------------------------------------------------------------
pnr/de1_binto7segment/de1_binto7segment_pins.tcl
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW
[
0
]
set_location_assignment PIN_L21 -to SW
[
1
]
set_location_assignment PIN_M22 -to SW
[
2
]
set_location_assignment PIN_V12 -to SW
[
3
]
set_location_assignment PIN_R20 -to LEDR
[
0
]
set_location_assignment PIN_R19 -to LEDR
[
1
]
set_location_assignment PIN_U19 -to LEDR
[
2
]
set_location_assignment PIN_Y19 -to LEDR
[
3
]
set_location_assignment PIN_J2 -to HEX0
[
0
]
set_location_assignment PIN_J1 -to HEX0
[
1
]
set_location_assignment PIN_H2 -to HEX0
[
2
]
set_location_assignment PIN_H1 -to HEX0
[
3
]
set_location_assignment PIN_F2 -to HEX0
[
4
]
set_location_assignment PIN_F1 -to HEX0
[
5
]
set_location_assignment PIN_E2 -to HEX0
[
6
]
# ----------------------------------------------------------------------------
pnr/de1_binto7segment/makefile
deleted
100644 → 0
View file @
950e33db
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME
=
binto7segment
PROJECT
=
de1_
$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
# Here the VHDL files for synthesis are defined.
include
../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/$(PROJECT)_structure.vhd
include
../makefile
pnr/de1_cntdn/de1_cntdn_pins.tcl
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY
[
0
]
set_location_assignment PIN_R21 -to KEY
[
1
]
set_location_assignment PIN_H12 -to GPO_1
[
0
]
set_location_assignment PIN_H13 -to GPO_1
[
1
]
set_location_assignment PIN_H14 -to GPO_1
[
2
]
set_location_assignment PIN_G15 -to GPO_1
[
3
]
set_location_assignment PIN_E14 -to GPO_1
[
4
]
set_location_assignment PIN_E15 -to GPO_1
[
5
]
# ----------------------------------------------------------------------------
pnr/de1_cntdn/makefile
deleted
100644 → 0
View file @
950e33db
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME
=
cntdn
PROJECT
=
de1_
$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
# Here the VHDL files for synthesis are defined.
include
../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/
$(PROJECT)
_structure.vhd
include
../makefile
pnr/de1_cntupen/de1_cntupen_pins.tcl
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY
[
0
]
set_location_assignment PIN_R21 -to KEY
[
1
]
set_location_assignment PIN_J2 -to HEX0
[
0
]
set_location_assignment PIN_J1 -to HEX0
[
1
]
set_location_assignment PIN_H2 -to HEX0
[
2
]
set_location_assignment PIN_H1 -to HEX0
[
3
]
set_location_assignment PIN_F2 -to HEX0
[
4
]
set_location_assignment PIN_F1 -to HEX0
[
5
]
set_location_assignment PIN_E2 -to HEX0
[
6
]
set_location_assignment PIN_H12 -to GPO_1
[
0
]
set_location_assignment PIN_H13 -to GPO_1
[
1
]
set_location_assignment PIN_H14 -to GPO_1
[
2
]
set_location_assignment PIN_G15 -to GPO_1
[
3
]
set_location_assignment PIN_E14 -to GPO_1
[
4
]
# ----------------------------------------------------------------------------
pnr/de1_cntupen/makefile
deleted
100644 → 0
View file @
950e33db
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME
=
cntupen
PROJECT
=
de1_
$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
# Here the VHDL files for synthesis are defined.
include
../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/binto7segment_truthtable.vhd
\
../../src/
$(PROJECT)
_structure.vhd
include
../makefile
pnr/de1_cntupen_1sec/de1_cntupen_1sec_pins.tcl
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY
set_location_assignment PIN_J2 -to HEX0
[
0
]
set_location_assignment PIN_J1 -to HEX0
[
1
]
set_location_assignment PIN_H2 -to HEX0
[
2
]
set_location_assignment PIN_H1 -to HEX0
[
3
]
set_location_assignment PIN_F2 -to HEX0
[
4
]
set_location_assignment PIN_F1 -to HEX0
[
5
]
set_location_assignment PIN_E2 -to HEX0
[
6
]
# ----------------------------------------------------------------------------
pnr/de1_cntupen_1sec/makefile
deleted
100644 → 0
View file @
950e33db
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME
=
cntupen
PROJECT
=
de1_
$(SIM_PROJECT_NAME)
_1sec
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
# Here the VHDL files for synthesis are defined.
include
../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/binto7segment_truthtable.vhd
\
../../src/cntdnmodm_rtl.vhd
\
../../src/
$(PROJECT)
_structure.vhd
include
../makefile
pnr/de1_cntupen_step/de1_cntupen_step_pins.tcl
deleted
100644 → 0
View file @
950e33db
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY
[
0
]
set_location_assignment PIN_R21 -to KEY
[
1
]
set_location_assignment PIN_J2 -to HEX0
[
0
]
set_location_assignment PIN_J1 -to HEX0
[
1
]
set_location_assignment PIN_H2 -to HEX0
[
2
]
set_location_assignment PIN_H1 -to HEX0
[
3
]
set_location_assignment PIN_F2 -to HEX0
[
4
]
set_location_assignment PIN_F1 -to HEX0
[
5
]
set_location_assignment PIN_E2 -to HEX0
[
6
]
# ----------------------------------------------------------------------------
pnr/de1_cntupen_step/makefile
deleted
100644 → 0
View file @
950e33db
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME
=
cntupen
PROJECT
=
de1_
$(SIM_PROJECT_NAME)
_step
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
# DEMMK
#FAMILY = "MAX II"
#DEVICE = EPM2210F324C3
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
# Here the VHDL files for synthesis are defined.
include
../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/binto7segment_truthtable.vhd
\
../../src/d_ff_rtl.vhd
\
../../src/rising_edge_detector_structure.vhd
\
../../src/
$(PROJECT)
_structure.vhd
include
../makefile
