Commit 7021203b authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

add play statemachine assignment

parent 00159813
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY[0]
set_location_assignment PIN_R21 -to KEY[1]
set_location_assignment PIN_U22 -to LEDG[0]
set_location_assignment PIN_U21 -to LEDG[1]
# ----------------------------------------------------------------------------
PROJECT = de1_play
# Here the VHDL files for synthesis are defined.
include ../../sim/de1_play/makefile.sources
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
PROJECT = de1_play
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
SYN_SOURCE_FILES = \
../../src/play_rtl.vhd \
../../src/rising_edge_detector_rtl.vhd \
../../src/count1s_rtl.vhd \
../../src/de1_play_structure.vhd
PROJECT = play
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
SYN_SOURCE_FILES = \
../../src/play_rtl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count1s is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_o : out std_ulogic);
end entity;
architecture rtl of count1s is
begin
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity de1_play is
port (
CLOCK_50 : in std_ulogic; -- 50 mhz clock
KEY : in std_ulogic_vector(1 downto 0); -- key(1..0)
LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0)
LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0)
);
end de1_play;
architecture structure of de1_play is
component count1s
port (
clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_o : out std_ulogic);
end component;
component rising_edge_detector
port (
clk : in std_ulogic;
rst_n : in std_ulogic;
x_i : in std_ulogic;
rise_o : out std_ulogic);
end component;
component play is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_i : in std_ulogic;
key_i : in std_ulogic;
led_o : out std_ulogic_vector(4 downto 0));
end component;
signal clk : std_ulogic;
signal rst_n : std_ulogic;
signal key_inv : std_ulogic;
signal key_edge : std_ulogic;
signal one_second_period : std_ulogic;
begin
-- connecting clock generator master clock of synchronous system
clk <= CLOCK_50;
-- connecting asynchronous system reset to digital system
rst_n <= KEY(0);
-- Invert the pushbutton for controlling play
key_inv <= not KEY(1);
LEDG <= not KEY; -- pushbutton on green LED
-- Rising Edge Detection for KEY1
rising_edge_detect_i0 : rising_edge_detector
port map (
clk => clk,
rst_n => rst_n,
x_i => key_inv,
rise_o => key_edge);
-- based on the 50 mhz clock, generates an enable signal of period t = 1 sec
count1s_i0 : count1s
port map (
clk => clk,
rst_n => rst_n,
onesec_o => one_second_period);
play_i0 : play
port map (
clk => clk,
rst_n => rst_n,
onesec_i => one_second_period,
key_i => key_edge,
led_o => LEDR);
end structure;
library ieee;
use ieee.std_logic_1164.all;
entity play is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_i : in std_ulogic;
key_i : in std_ulogic;
led_o : out std_ulogic_vector(4 downto 0));
end play;
architecture rtl of play is
type state_t is (start_s,one_s,chance_s,four_s,last_s,hit0_s,hit1_s);
signal current_state,next_state : state_t;
begin
current_state <= start_s when rst_n = '0' else next_state when rising_edge(clk);
next_p : process(current_state, onesec_i, key_i)
begin
next_state <= current_state;
led_o <= "00000";
case current_state is
when start_s =>
led_o <= "10000";
if onesec_i = '1' then
next_state <= one_s;
end if;
when one_s =>
led_o <= "01000";
if onesec_i = '1' then
next_state <= chance_s;
end if;
when chance_s =>
led_o <= "00100";
if key_i = '1' then
next_state <= hit0_s;
elsif onesec_i = '1' then
next_state <= four_s;
end if;
when four_s =>
led_o <= "00010";
if onesec_i = '1' then
next_state <= last_s;
end if;
when last_s =>
led_o <= "00001";
if onesec_i = '1' then
next_state <= start_s;
end if;
when hit0_s =>
led_o <= "10000";
if key_i = '1' then
next_state <= chance_s;
elsif onesec_i = '1' then
next_state <= hit1_s;
end if;
when hit1_s =>
led_o <= "00001";
if key_i = '1' then
next_state <= chance_s;
elsif onesec_i = '1' then
next_state <= hit0_s;
end if;
when others => null;
end case;
end process;
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity rising_edge_detector is
port (
clk : in std_ulogic;
rst_n : in std_ulogic;
x_i : in std_ulogic;
rise_o : out std_ulogic
);
end rising_edge_detector;
architecture rtl of rising_edge_detector is
signal q0, q1 : std_ulogic;
begin
-- Flipflops
q0 <= '0' when rst_n = '0' else x_i when rising_edge(clk);
q1 <= '0' when rst_n = '0' else q0 when rising_edge(clk);
rise_o <= q0 and not q1;
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity t_de1_play is
end t_de1_play;
architecture tbench of t_de1_play is
component de1_play is
port (
CLOCK_50 : in std_ulogic; -- 50 mhz clock
KEY : in std_ulogic_vector(1 downto 0); -- key(1..0)
LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0)
LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0)
);
end component;
-- definition of a clock period
constant period : time := 10 ns;
-- switch for clock generator
signal clken_p : boolean := true;
signal clk_i : std_ulogic;
signal rst_ni : std_ulogic;
signal key : std_ulogic;
signal ledr : std_ulogic_vector(4 downto 0);
begin
-- clock generation
clock_proc : process
begin
while clken_p loop
clk_i <= '0'; wait for period/2;
clk_i <= '1'; wait for period/2;
end loop;
wait;
end process;
-- initial reset, always necessary at the beginning of a simulation
reset : rst_ni <= '0', '1' AFTER period;
stimuli_p : process
begin
key <= '1';
wait until rst_ni = '1';
wait for 15*period;
wait until falling_edge(clk_i) and ledr = "00010";
key <= '0';
wait until falling_edge(clk_i) and ledr = "00100";
wait for period;
key <= '1';
wait for period;
key <= '0';
wait for 1 * period;
key <= '1';
wait until falling_edge(clk_i) and ledr = "10000";
for i in 0 to 100 loop
wait until falling_edge(clk_i);
assert ledr = "10000" or ledr = "00001" report "hit error";
end loop;
wait until falling_edge(clk_i) and ledr = "00001";
clken_p <= false;
wait;
end process stimuli_p;
de1_play_i0 : de1_play
port map (
CLOCK_50 => clk_i,
KEY(0) => rst_ni,
KEY(1) => key,
LEDR => ledr);
simstop_p : process
begin
wait on clken_p for 2000 ns;
assert not clken_p report "Simulation failed due to timeout" severity failure;
wait;
end process;
end tbench;
-------------------------------------------------------------------------------
-- module : de1_play
-------------------------------------------------------------------------------
-- author : Friedrich Beckmann
-- company : university of applied sciences augsburg
-------------------------------------------------------------------------------
-- description: test the module play on a de1 prototype board
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t_play is
end t_play;
architecture tbench of t_play is
component play is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_i : in std_ulogic;
key_i : in std_ulogic;
led_o : out std_ulogic_vector(4 downto 0));
end component;
-- definition of a clock period
constant period : time := 10 ns;
-- switch for clock generator
signal clken_p : boolean := true;
signal clk_i : std_ulogic;
signal rst_ni : std_ulogic;
signal key_edge : std_ulogic;
signal one_second_period : std_ulogic;
signal ledr : std_ulogic_vector(4 downto 0);
begin
-- clock generation
clock_proc : process
begin
while clken_p loop
clk_i <= '0'; wait for period/2;
clk_i <= '1'; wait for period/2;
end loop;
wait;
end process;
onesec_p : process
begin
one_second_period <= '0';
wait until falling_edge(clk_i);
wait until falling_edge(clk_i);
one_second_period <= '1';
wait until falling_edge(clk_i);
end process;
-- initial reset, always necessary at the beginning of a simulation
reset : rst_ni <= '0', '1' AFTER period;
stimuli_p : process
begin
key_edge <= '0';
wait until rst_ni = '1';
wait for 15*period;
wait until falling_edge(clk_i) and ledr = "00010";
key_edge <= '1';
wait until falling_edge(clk_i) and ledr = "00100";
wait for period;
key_edge <= '0';
wait for 5*period;
wait until falling_edge(clk_i) and ledr = "00001";
key_edge <= '1';
wait for 5*period;
wait until falling_edge(clk_i) and ledr = "00100";
key_edge <= '0';
wait for 15*period;
clken_p <= false;
wait;
end process stimuli_p;
play_i0 : play
port map (
clk => clk_i,
rst_n => rst_ni,
onesec_i => one_second_period,
key_i => key_edge,
led_o => ledr);
simstop_p : process
begin
wait on clken_p for 800 ns;
assert not clken_p report "Simulation failed due to timeout" severity failure;
wait;
end process;
end tbench;
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment