pnr/makefile: make dedicated target for sdc file

with this change the sdc file target can be overwritten in the
project specific makefile.

pnr/makefile

@@ -22,23 +22,23 @@ help:
 	@echo '  "make quartus" to start quartus graphical user interface'
 	@echo '  "make clean" to remove all generated files'
 
+$(PROJECT).sdc:
+	# create a default timing constraint file assuming CLOCK_50
+	echo "create_clock -period 20.000 -name CLOCK_50 CLOCK_50" > $(PROJECT).sdc
+	echo "set_input_delay -clock CLOCK_50 2 [all_inputs]" >> $(PROJECT).sdc
+	echo "set_output_delay -clock CLOCK_50 2 [all_outputs]" >> $(PROJECT).sdc
 
 qproject: $(PROJECT).qpf
 
-$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl
+$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl $(PROJECT).sdc
 	# assign VHDL design files
 	rm -rf quartus_vhdl_source_files.tcl
 	for source_file in $(SOURCE_FILES); do \
 		echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \
 	done
-	# create a default timing constraint file assuming CLOCK_50
-	echo "create_clock -period 20.000 -name CLOCK_50 CLOCK_50" > $(PROJECT).sdc
-	echo "set_input_delay -clock CLOCK_50 2 [all_inputs]" >> $(PROJECT).sdc
-	echo "set_output_delay -clock CLOCK_50 2 [all_outputs]" >> $(PROJECT).sdc
 	# just create a quartus project
 	quartus_sh -t ../../scripts/create_quartus_project_settings.tcl -projectname $(PROJECT)
 
-
 compile: flowsummary.log
 
 flowsummary.log: $(PROJECT).qpf ../../scripts/quartus_project_flow.tcl