added projects of lab exercise #3

pnr/de1_cntdn/de1_cntdn_pins.tcl

+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_H12 -to GPO_1[0]
+set_location_assignment PIN_H13 -to GPO_1[1]
+set_location_assignment PIN_H14 -to GPO_1[2]
+set_location_assignment PIN_G15 -to GPO_1[3]
+set_location_assignment PIN_E14 -to GPO_1[4]
+set_location_assignment PIN_E15 -to GPO_1[5]
+# ----------------------------------------------------------------------------

pnr/de1_cntdn/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = cntdn
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+

pnr/de1_cntupen/de1_cntupen_pins.tcl

+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_J2 -to HEX0[0] 
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_H12 -to GPO_1[0]
+set_location_assignment PIN_H13 -to GPO_1[1]
+set_location_assignment PIN_H14 -to GPO_1[2]
+set_location_assignment PIN_G15 -to GPO_1[3]
+set_location_assignment PIN_E14 -to GPO_1[4]
+# ----------------------------------------------------------------------------

pnr/de1_cntupen/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = cntupen
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/binto7segment_truthtable.vhd \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+

pnr/de1_cntupen_1sec/de1_cntupen_1sec_pins.tcl

+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY
+set_location_assignment PIN_J2 -to HEX0[0] 
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+# ----------------------------------------------------------------------------

pnr/de1_cntupen_1sec/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = cntupen
+PROJECT = de1_$(SIM_PROJECT_NAME)_1sec
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/binto7segment_truthtable.vhd \
+../../src/cntdnmodm_rtl.vhd \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+

pnr/de1_cntupen_step/de1_cntupen_step_pins.tcl

+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_J2 -to HEX0[0] 
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+# ----------------------------------------------------------------------------

pnr/de1_cntupen_step/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = cntupen
+PROJECT = de1_$(SIM_PROJECT_NAME)_step
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/binto7segment_truthtable.vhd \
+../../src/d_ff_rtl.vhd \
+../../src/rising_edge_detector_structure.vhd \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+

sim/cnt4up/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = cnt4up
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+

sim/cnt4up/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/d_ff_rtl.vhd \
+../../src/dreg_structure.vhd \
+../../src/add4_rtl.vhd \
+../../src/cnt4up_structure.vhd \
+
+# do not delete this line
\ No newline at end of file

sim/cntdn/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = cntdn
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+

sim/cntdn/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/dregen_rtl.vhd \
+../../src/add4_rtl.vhd \
+../../src/cntdn_structure.vhd \
+
+# do not delete this line
\ No newline at end of file

sim/cntupen/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = cntupen
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+

sim/cntupen/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/dregen_rtl.vhd \
+../../src/add4_rtl.vhd \
+../../src/cntupen_structure.vhd \
+
+# do not delete this line
\ No newline at end of file

sim/rising_edge_detector/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = rising_edge_detector
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+

sim/rising_edge_detector/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/d_ff_rtl.vhd \
+../../src/rising_edge_detector_structure.vhd \
+

src/cnt4up_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : cnt4up
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 4-Bit Up-Counter
+--              including a low-active asynchronous reset input rst_ni
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY cnt4up IS
+  PORT (clk_i   : IN  std_ulogic;
+        rst_ni  : IN  std_ulogic;
+        count_o : OUT std_ulogic_vector(3 DOWNTO 0)
+        );
+END cnt4up;
+
+ARCHITECTURE structure OF cnt4up IS
+
+  COMPONENT dreg
+    PORT (
+      clk_i  : IN  std_ulogic;
+      rst_ni : IN  std_ulogic;
+      d_i    : IN  std_ulogic_vector(3 DOWNTO 0);
+      q_o    : OUT std_ulogic_vector(3 DOWNTO 0));
+  END COMPONENT;
+
+  COMPONENT add4
+    PORT (
+      a_i   : IN  std_ulogic_vector(3 DOWNTO 0);
+      b_i   : IN  std_ulogic_vector(3 DOWNTO 0);
+      ci_i  : IN  std_ulogic;
+      sum_o : OUT std_ulogic_vector(3 DOWNTO 0);
+      co_o  : OUT std_ulogic);
+  END COMPONENT;
+
+  SIGNAL next_state, current_state : std_ulogic_vector(3 DOWNTO 0);
+  
+BEGIN
+
+  incrementer : ENTITY work.add4(rtl)
+    PORT MAP (
+      a_i   => B"0001",
+      b_i   => current_state,
+      ci_i  => '0',
+      sum_o => next_state,
+      co_o  => OPEN);
+
+  state_register : ENTITY work.dreg(structure)
+    PORT MAP (
+      clk_i  => clk_i,
+      rst_ni => rst_ni,
+      d_i    => next_state,
+      q_o    => current_state);
+
+  counter_output : count_o <= current_state;
+
+END structure;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+