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Friedrich Beckmann
digitaltechnikpraktikum
Commits
7e4c9160
Commit
7e4c9160
authored
Mar 10, 2021
by
Friedrich Beckmann
Browse files
added default timing constraint for CLOCK_50
parent
ecc3a212
Changes
1
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pnr/makefile
View file @
7e4c9160
...
...
@@ -31,6 +31,10 @@ $(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tc
for
source_file
in
$(SOURCE_FILES)
;
do
\
echo
set_global_assignment
-name
VHDL_FILE
$$
source_file
>>
quartus_vhdl_source_files.tcl
;
\
done
# create a default timing constraint file assuming CLOCK_50
echo
"create_clock -period 20.000 -name CLOCK_50 CLOCK_50"
>
$(PROJECT)
.sdc
echo
"set_input_delay -clock CLOCK_50 2 [all_inputs]"
>>
$(PROJECT)
.sdc
echo
"set_output_delay -clock CLOCK_50 2 [all_outputs]"
>>
$(PROJECT)
.sdc
# just create a quartus project
quartus_sh
-t
../../scripts/create_quartus_project_settings.tcl
-projectname
$(PROJECT)
...
...
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