added default timing constraint for CLOCK_50

pnr/makefile

@@ -31,6 +31,10 @@ $(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tc
 	for source_file in $(SOURCE_FILES); do \
 		echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \
 	done
+	# create a default timing constraint file assuming CLOCK_50
+	echo "create_clock -period 20.000 -name CLOCK_50 CLOCK_50" > $(PROJECT).sdc
+	echo "set_input_delay -clock CLOCK_50 2 [all_inputs]" >> $(PROJECT).sdc
+	echo "set_output_delay -clock CLOCK_50 2 [all_outputs]" >> $(PROJECT).sdc
 	# just create a quartus project
 	quartus_sh -t ../../scripts/create_quartus_project_settings.tcl -projectname $(PROJECT)