added cnt15 with sim and pnr

pnr/de1_cnt15/de1_cnt15_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R22 -to KEY[0] 
+set_location_assignment PIN_R21 -to KEY[1] 
+set_location_assignment PIN_T22 -to KEY[2] 
+set_location_assignment PIN_T21 -to KEY[3] 
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_J2  -to HEX0[0]
+set_location_assignment PIN_J1  -to HEX0[1]
+set_location_assignment PIN_H2  -to HEX0[2]
+set_location_assignment PIN_H1  -to HEX0[3]
+set_location_assignment PIN_F2  -to HEX0[4]
+set_location_assignment PIN_F1  -to HEX0[5]
+set_location_assignment PIN_E2  -to HEX0[6]
+
+
+
+
+
+
+

pnr/de1_cnt15/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+SIM_PROJECT_NAME = de1_cnt15
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

sim/de1_cnt15/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+PROJECT = de1_cnt15
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+
+

sim/de1_cnt15/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/de1_cnt15_rtl.vhd \
+../../src/cnt15_rtl.vhd \
+../../src/bin2seg_rtl.vhd
+
+# do not delete this line
+# -----------------------------------------------------------------------------

src/cnt15_rtl.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Loadable downcounter which stops when cnt is 0
+-- The done_o output is 1, when cnt is 0;
+-- When ld_i is '1', the counter is loaded with a startvalue of 13
+-- The cnt_o output shows the current value of the counter
+
+entity cnt15 is 
+port ( clk    : in      std_ulogic;
+       rst_n  : in      std_ulogic; 
+       ld_i   : in      std_ulogic;
+       done_o : out     std_ulogic;
+       cnt_o  : out     std_ulogic_vector(3 downto 0)); 
+end entity;
+
+architecture rtl of cnt15 is 
+
+begin
+  
+end architecture rtl;

src/de1_cnt15_rtl.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity de1_cnt15 is 
+port ( SW       : in  std_ulogic_vector(9 downto 0);
+       KEY      : in  std_ulogic_vector(3 downto 0);
+       HEX0     : out std_ulogic_vector(6 downto 0); 
+       LEDG     : out std_ulogic_vector(7 downto 0);   -- green LEDs
+       LEDR     : out std_ulogic_vector(9 downto 0));  -- red LEDs
+end entity;
+
+architecture rtl of de1_cnt15 is
+
+  component bin2seg is
+    port (bin_i  : in  std_ulogic_vector(3 downto 0);
+           seg_o : out std_ulogic_vector(6 downto 0));  
+  end component;
+
+  component cnt15 is
+    port (clk     : in  std_ulogic;
+           rst_n  : in  std_ulogic;
+           ld_i   : in  std_ulogic;
+           done_o : out std_ulogic;
+           cnt_o  : out std_ulogic_vector(3 downto 0)); 
+  end component;
+
+  signal cnt : std_ulogic_vector(3 downto 0);
+
+begin
+
+  cnt15_i0 : cnt15
+    port map (
+      clk    => KEY(1),
+      rst_n  => KEY(0),
+      ld_i   => SW(0),
+      done_o => LEDG(2),
+      cnt_o  => cnt);
+
+  bin2seg_i0 : bin2seg
+    port map (
+      bin_i => cnt,
+      seg_o => HEX0);
+
+  LEDR <= SW;
+  LEDG(1 downto 0) <= KEY(1 downto 0);
+  LEDG(7 downto 4) <= cnt;
+  LEDG(3) <= '0'; 
+    
+end architecture rtl;

src/t_de1_cnt15.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity t_de1_cnt15 is
+end; 
+
+architecture tbench of t_de1_cnt15 is
+
+  component de1_cnt15 is 
+    port ( SW       : in  std_ulogic_vector(9 downto 0);
+           KEY      : in  std_ulogic_vector(3 downto 0);
+           HEX0     : out std_ulogic_vector(6 downto 0);
+           LEDG     : out std_ulogic_vector(7 downto 0);   -- green LEDs
+           LEDR     : out std_ulogic_vector(9 downto 0));  -- red LEDs
+  end component;
+
+  signal redleds                : std_ulogic_vector(9 downto 0);
+  signal greenleds              : std_ulogic_vector(7 downto 0);
+  signal clk, rst_n             : std_ulogic;
+  signal simstop                : boolean := false;
+  signal d                      : std_ulogic;
+
+begin
+
+  de1_cnt15_i0 : de1_cnt15
+    port map (
+      SW(0)               => d,
+      SW(9 downto 1)      => "000000000",
+      KEY(0)              => rst_n,
+      KEY(1)              => clk,
+      KEY(3 downto 2)     => "00",
+      LEDG                => greenleds, 
+      LEDR                => redleds);
+
+  rst_n <= '1', '0' after 20 ns, '1' after 40 ns;
+
+  clk_p : process
+    begin
+      clk <= '0';
+      wait for 10 ns;
+      clk <= '1';
+      wait for 10 ns;
+      if simstop then
+        wait;
+      end if;
+    end process clk_p;
+
+  -- This is the process where the switches are switched.
+  schalter : process
+  begin
+    d <= '0';
+    wait until rising_edge(rst_n);
+    wait until falling_edge(clk);
+    d <= '1';
+    wait for 100 ns;
+    d <= '0';
+    wait for 400 ns;
+    simstop <= true; 
+    wait; 
+  end process schalter;
+
+end; -- architecture