added design add4

pnr/de1_add4/de1_add4_pins.tcl

+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_J2 -to HEX0[0] 
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_H12 -to GPO_1[0]
+set_location_assignment PIN_H13 -to GPO_1[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+# ----------------------------------------------------------------------------

pnr/de1_add4/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = add4
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/binto7segment_truthtable.vhd \
+../../src/$(PROJECT)_structure.vhd
+
+include ../makefile
+
+

sim/add4/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = add4
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+

sim/add4/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/add1_truthtable.vhd \
+../../src/add4_structure.vhd \

src/add4_rtl.vhd

+-------------------------------------------------------------------------------
+-- Module     : add4
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 4-bit adder
+--              function modelled by '+'-operator
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+ENTITY add4 IS
+  PORT (a_i   : IN  std_ulogic_vector(3 DOWNTO 0);         -- operand a
+        b_i   : IN  std_ulogic_vector(3 DOWNTO 0);         -- operand b
+        ci_i  : IN  std_ulogic;         -- carry in
+        sum_o : OUT std_ulogic_vector(3 DOWNTO 0);         -- sum
+        co_o  : OUT std_ulogic          -- carry out
+        );
+END add4;
+
+ARCHITECTURE rtl OF add4 IS
+
+  SIGNAL temp_sum : unsigned(4 DOWNTO 0);
+
+BEGIN
+
+--  (co_o,sum_o) <= ('0' & unsigned(a_i)) + unsigned(b_i) + unsigned'(0 => ci_i);
+
+  
+  temp_sum <= ('0' & unsigned(a_i)) + unsigned(b_i) + unsigned'(0 => ci_i);
+
+  sum_o <= std_ulogic_vector(temp_sum(3 DOWNTO 0));
+
+  co_o <= temp_sum(4);
+
+END rtl;
+
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+

src/add4_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : add4
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: 4-bit adder
+--              function modelled by cascading 1-bit adder modules
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ENTITY add4 IS
+  PORT (a_i   : IN  std_ulogic_vector(3 DOWNTO 0);  -- operand a
+        b_i   : IN  std_ulogic_vector(3 DOWNTO 0);  -- operand b
+        ci_i  : IN  std_ulogic;                     -- carry in
+        sum_o : OUT std_ulogic_vector(3 DOWNTO 0);  -- sum
+        co_o  : OUT std_ulogic                      -- carry out
+        );
+END add4;
+
+ARCHITECTURE structure OF add4 IS
+
+  COMPONENT add1
+    PORT(a_i   : IN  std_ulogic;
+         b_i   : IN  std_ulogic;
+         ci_i  : IN  std_ulogic;
+         sum_o : OUT std_ulogic;
+         co_o  : OUT std_ulogic
+         );
+  END COMPONENT;
+
+  SIGNAL carry0 : std_ulogic;
+  SIGNAL carry1 : std_ulogic;
+  SIGNAL carry2 : std_ulogic;
+
+
+BEGIN
+
+  inst0 : add1
+    PORT MAP(a_i   => a_i(0),
+             b_i   => b_i(0),
+             ci_i  => ci_i,
+             sum_o => sum_o(0),
+             co_o  => carry0);
+
+  inst1 : add1
+    PORT MAP(a_i   => a_i(1),
+             b_i   => b_i(1),
+             ci_i  => carry0,
+             sum_o => sum_o(1),
+             co_o  => carry1);
+
+  inst2 : add1
+    PORT MAP(a_i   => a_i(2),
+             b_i   => b_i(2),
+             ci_i  => carry1,
+             sum_o => sum_o(2),
+             co_o  => carry2);
+
+  inst3 : add1
+    PORT MAP(a_i   => a_i(3),
+             b_i   => b_i(3),
+             ci_i  => carry2,
+             sum_o => sum_o(3),
+             co_o  => co_o);
+
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------

src/binto7segment_stimuli.vhd

+-------------------------------------------------------------------------------
+-- Module     : binto7segment_stimuli
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: stimuli for verification of binary-to-7-segment decoder
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY binto7segment_stimuli IS
+  PORT (
+    stimuli_o : OUT std_ulogic_vector(3 DOWNTO 0)
+    );
+END binto7segment_stimuli;
+
+ARCHITECTURE stimuli OF binto7segment_stimuli IS
+
+  -- definition of a clock period
+  CONSTANT period : time := 10 ns;
+
+BEGIN
+  
+  stimuli_p : PROCESS
+  BEGIN
+    stimuli_o <= "0000";
+    WAIT FOR period;
+    stimuli_o <= "0001";
+    WAIT FOR period;
+    stimuli_o <= "0010";
+    WAIT FOR period;
+    stimuli_o <= "0011";
+    WAIT FOR period;
+    stimuli_o <= "0100";
+    WAIT FOR period;
+    stimuli_o <= "0101";
+    WAIT FOR period;
+    stimuli_o <= "0110";
+    WAIT FOR period;
+    stimuli_o <= "0111";
+    WAIT FOR period;
+    stimuli_o <= "1000";
+    WAIT FOR period;
+    stimuli_o <= "1001";
+    WAIT FOR period;
+    stimuli_o <= "1010";
+    WAIT FOR period;
+    stimuli_o <= "1011";
+    WAIT FOR period;
+    stimuli_o <= "1100";
+    WAIT FOR period;
+    stimuli_o <= "1101";
+    WAIT FOR period;
+    stimuli_o <= "1110";
+    WAIT FOR period;
+    stimuli_o <= "1111";
+    WAIT FOR period;
+    WAIT;
+  END PROCESS;
+
+END stimuli;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
+

src/de1_add1_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : de1_add1
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: test the module add1 on a DE1 prototype board
+--              connecting device under test (DUT) add1
+--              to input/output signals of the DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_add1 IS
+  PORT (
+    SW   : IN  std_ulogic_vector(2 DOWNTO 0);  -- Toggle Switch[2:0]
+    LEDR : OUT std_ulogic_vector(1 DOWNTO 0)   -- LED Red[1:0]  
+    );
+END de1_add1;
+
+ARCHITECTURE structure OF de1_add1 IS
+
+  COMPONENT add1
+    PORT (
+      a_i   : IN  std_ulogic;
+      b_i   : IN  std_ulogic;
+      ci_i  : IN  std_ulogic;
+      sum_o : OUT std_ulogic;
+      co_o  : OUT std_ulogic);
+  END COMPONENT;
+
+BEGIN
+
+  -- connecting device under test with peripheral elements
+  DUT : add1
+    PORT MAP (
+      a_i   => SW(0),
+      b_i   => SW(1),
+      ci_i  => SW(2),
+      sum_o => LEDR(0),
+      co_o  => LEDR(1)
+      );
+
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------

src/de1_add4_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : de1_add4
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: test the module add4 on a DE1 prototype board
+--              connecting device under test (DUT) add4
+--              to input/output signals of the DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_add4 IS
+  PORT (
+    SW   : IN  std_ulogic_vector(8 DOWNTO 0);  -- Toggle Switch[8:0]
+    LEDR : OUT std_ulogic_vector(8 DOWNTO 0);  -- LED Red[8:0]
+    LEDG : OUT std_ulogic_vector(4 DOWNTO 0);  -- LED Green[3:0]
+    HEX0 : OUT std_ulogic_vector(6 DOWNTO 0);  -- Seven Segment Digit 0
+    HEX1 : OUT std_ulogic_vector(6 DOWNTO 0);  -- Seven Segment Digit 1
+    HEX2 : OUT std_ulogic_vector(6 DOWNTO 0);  -- Seven Segment Digit 2
+
+    -- Ports for measurement of longest path through module
+    CLOCK_50 : IN  std_ulogic;                    -- 50 MHz Clock
+    GPO_1    : OUT std_ulogic_vector(1 DOWNTO 0)  -- Output Connector GPIO_1
+                                                  -- GPO_1[0] = ci_i
+                                                  -- GPO_1[1] = co_o
+
+    );
+END de1_add4;
+
+ARCHITECTURE structure OF de1_add4 IS
+
+  COMPONENT binto7segment
+    PORT (
+      bin_i      : IN  std_ulogic_vector(3 DOWNTO 0);
+      segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
+  END COMPONENT;
+
+  COMPONENT add4
+    PORT (
+      a_i   : IN  std_ulogic_vector(3 DOWNTO 0);
+      b_i   : IN  std_ulogic_vector(3 DOWNTO 0);
+      ci_i  : IN  std_ulogic;
+      sum_o : OUT std_ulogic_vector(3 DOWNTO 0);
+      co_o  : OUT std_ulogic);
+  END COMPONENT;
+
+  SIGNAL a   : std_ulogic_vector(3 DOWNTO 0);
+  SIGNAL b   : std_ulogic_vector(3 DOWNTO 0);
+  SIGNAL ci  : std_ulogic;
+  SIGNAL sum : std_ulogic_vector(3 DOWNTO 0);
+  SIGNAL co  : std_ulogic;
+
+BEGIN
+
+  -- Modifications for measurement of longest path through module
+  GPO_1(0) <= ci;
+  GPO_1(1) <= co;
+  -- ci       <= CLOCK_50;               -- uncommend if connected by SW(0)
+  
+  -- connecting switches to operands
+  ci <= SW(0);                        -- uncomment, if connected by CLOCK_50
+  a <= SW(4 DOWNTO 1);
+  b <= SW(8 DOWNTO 5);
+
+  -- connecting operands to LEDs
+  LEDR(0)          <= SW(0);
+  LEDR(4 DOWNTO 1) <= SW(4 DOWNTO 1);
+  LEDR(8 DOWNTO 5) <= SW(8 DOWNTO 5);
+
+  -- connecting device under test with peripheral elements
+  DUT : add4
+    PORT MAP (
+      a_i   => a,
+      b_i   => b,
+      ci_i  => ci,
+      sum_o => sum,
+      co_o  => co);
+
+  -- connecting results to LEDs and HEX displays
+  LEDG(3 DOWNTO 0) <= sum;
+  LEDG(4)          <= co;
+
+  operand_a : binto7segment
+    PORT MAP (
+      bin_i      => a,
+      segments_o => HEX0);
+
+  operand_b : binto7segment
+    PORT MAP (
+      bin_i      => b,
+      segments_o => HEX1);
+
+  result_sum : binto7segment
+    PORT MAP (
+      bin_i      => sum,
+      segments_o => HEX2);
+
+
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------

src/de1_binto7segment_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : de1_binto7segment
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: test the module binto7segment on a DE1 prototype board
+--              connecting device under test (DUT) binto7segment
+--              to input/output signals of the DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_binto7segment IS
+  PORT (
+    SW        : IN    std_ulogic_vector(3 DOWNTO 0);  -- Toggle Switch[3:0]
+    LEDR      : OUT   std_ulogic_vector(3 DOWNTO 0);  -- LED Red[3:0]  
+    HEX0      : OUT   std_ulogic_vector(6 DOWNTO 0)   -- Seven Segment Digit 0 
+    );
+END de1_binto7segment;
+
+ARCHITECTURE structure OF de1_binto7segment IS
+  
+  COMPONENT binto7segment
+    PORT (
+      bin_i      : IN  std_ulogic_vector(3 DOWNTO 0);
+      segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
+  END COMPONENT;
+
+BEGIN
+
+  -- connecting device under test with peripheral elements
+  DUT : binto7segment
+    PORT MAP (
+      bin_i      => SW,
+      segments_o => HEX0);
+
+  -- connect switches to red LEDs
+  LEDR <= SW;
+
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------

src/de1_mux2to1_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : de1_mux2to1
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: test the module add1 on a DE1 prototype board
+--              connecting device under test (DUT) add1
+--              to input/output signals of the DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_mux2to1 IS
+  PORT (
+    SW   : IN  std_ulogic_vector(2 DOWNTO 0);  -- Toggle Switch[2:0]
+    LEDR : OUT std_ulogic   -- LED Red[0]  
+    );
+END de1_mux2to1;
+
+ARCHITECTURE structure OF de1_mux2to1 IS
+
+  COMPONENT mux2to1
+    PORT (
+      a_i   : IN  std_ulogic;
+      b_i   : IN  std_ulogic;
+      sel_i : IN  std_ulogic;
+      y_o   : OUT std_ulogic);
+  END COMPONENT;
+
+BEGIN
+
+  -- connecting device under test with peripheral elements
+  DUT : mux2to1
+    PORT MAP (
+      a_i   => SW(0),
+      b_i   => SW(1),
+      sel_i => SW(2),
+      y_o   => LEDR);
+  
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------

src/t_add1.vhd

+-------------------------------------------------------------------------------
+-- Module     : t_add1
+-------------------------------------------------------------------------------
+-- Author     :   <haf@fh-augsburg.de>
+-- Company    : University of Applied Sciences Augsburg
+-- Copyright (c) 2011   <haf@fh-augsburg.de>
+-------------------------------------------------------------------------------
+-- Description: Testbench for design "add1"
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-------------------------------------------------------------------------------
+
+ENTITY t_add1 IS
+END t_add1;
+
+-------------------------------------------------------------------------------
+
+ARCHITECTURE tbench OF t_add1 IS
+
+  COMPONENT add1
+    PORT (
+      a_i   : IN  std_ulogic;
+      b_i   : IN  std_ulogic;