added conditional signal assignment as multiplexer

src/ledcomb_rtl.vhd

@@ -10,7 +10,7 @@ end entity ledcomb;
 
 architecture rtl of ledcomb is
 
-  signal s0, s1 : std_ulogic; 
+  signal s0, s1, s3 : std_ulogic;
 
 begin
 
@@ -30,11 +30,17 @@ begin
   LEDG(3) <= s0 or s1;
 
   ----------------------------------------------------------------------------
-  -- Truthtable direct method (if you have a truthtable...)
+  -- Multiplexer via conditional signal assignment
+  ----------------------------------------------------------------------------
+
+  LEDG(4) <= s3 when SW(3) = '1' else s1;
+
+  ----------------------------------------------------------------------------
+  -- Truthtable direct method (if you have a truthtable...) as with ... select
   ----------------------------------------------------------------------------
 
   with SW(9 downto 5) select
-    LEDG(4) <= 
+    s3 <=
     '1' when "11111",
     '1' when "00000",
     '1' when "10101"|"01010",  -- select more than one condition
@@ -54,5 +60,5 @@ begin
   -- One select value must be "others" because all possible 
   -- combinations must be listed and std_ulogic also has other possible values
   -- than '0' and '1', e.g. 'Z'. However, these values only exist in simulation
- 
+
 end architecture rtl;