first

.gitignore

+# Ignore files for git
+
+# Emacs backup files
+*~
+*.bak
+

pnr/de1_binto7segment/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: see end of file
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+# 
+# Prerequisite: - mandatory design directory structure (see end of file)
+#               - scripts/quartus_project_settings.tcl
+#               - scripts/de1_$(PROJECT)_pins.tcl
+#
+# - modify and copy it to pnr/de1_(PROJECT)/makefile
+# - specify the name of the design (PROJECT)
+# - and the list of source files used (SOURCE_FILES)
+###################################################################
+PROTOTYPE = de1
+PROJECT = de1_binto7segment
+SOURCE_FILES = \
+../../src/binto7segment_stimuli.vhd \
+../../src/binto7segment_truthtable.vhd \
+../../src/$(PROJECT)_structure.vhd
+ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf 
+
+
+###################################################################
+# Main Targets
+#
+###################################################################
+
+help:
+	@echo '"make" does intentionally nothing. Type:'
+	@echo '  "make clean" to remove all generated files'
+	@echo '  "make project" to create a new quartus project'
+	@echo '  "make compile" to process through all design steps: map, fit, asm'
+	@echo '  "make prog" to configure programmable device'
+	@echo '  "make quartus" to start quartus graphical user interface'
+	
+compile: smart.log $(PROJECT).asm.rpt
+
+project: 
+	# create quartus project
+	quartus_sh -t ../../scripts/quartus_project_settings.tcl -projectname $(PROJECT)
+	# assign VHDL design files
+	for source_file in $(SOURCE_FILES); do \
+		quartus_sh --set VHDL_FILE=$$source_file $(PROJECT); \
+	done
+	# assign pins
+	$ if [ -f ../../scripts/$(PROJECT)_pins.tcl ]; then quartus_sh -t ../../scripts/$(PROJECT)_pins.tcl -projectname $(PROJECT); fi
+	
+clean:
+	rm -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary
+
+map: smart.log $(PROJECT).map.rpt
+fit: smart.log $(PROJECT).fit.rpt
+asm: smart.log $(PROJECT).asm.rpt
+smart: smart.log
+
+prog:
+	quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).sof"
+
+quartus: 
+	# create quartus project
+	quartus $(PROJECT).qpf &
+
+
+###################################################################
+# Target implementations
+###################################################################
+
+STAMP = echo done >
+
+$(PROJECT).map.rpt: map.chg $(SOURCE_FILES) 
+	quartus_map $(PROJECT)
+	$(STAMP) fit.chg
+
+$(PROJECT).fit.rpt: fit.chg $(PROJECT).map.rpt
+	quartus_fit $(PROJECT)
+	$(STAMP) asm.chg
+	$(STAMP) sta.chg
+
+$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
+	quartus_asm $(ASM_ARGS) $(PROJECT)
+
+
+smart.log: $(ASSIGNMENT_FILES)
+	quartus_sh --determine_smart_action $(PROJECT) > smart.log
+
+###################################################################
+# Project initialization
+###################################################################
+
+$(ASSIGNMENT_FILES):
+	quartus_sh --prepare $(PROJECT)
+
+map.chg:
+	$(STAMP) map.chg
+fit.chg:
+	$(STAMP) fit.chg
+asm.chg:
+	$(STAMP) asm.chg
+
+	
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       de1_mux2to1_structure.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       
+## +---pnr
+## |   +---de1_mux2to1
+## |           makefile
+## |           de1_mux2to1.qpf
+## |           de1_mux2to1.qpf
+## |
+## +---scripts
+## |       quartus_project_settings.tcl
+## |       makefile.quartus_template
+## |       makefile.modelsim_template
+## |       de1_mux2to1_pins.tcl
+## |       modelsim_project_settings.tcl
+## |       modelsim.ini
+## |       de1_pin_assignments_minimumio.csv
+## |       de1_pin_assignments_minimumio.tcl
+## |       
+## \---sim
+##     +---mux2to1
+##             makefile
+##             mux2to1.mpf
+##             modelsim.ini
+## 
+## ----------------------------------------------------------------------------
+## Modifications: makefile template from Altera Quartus scripting modified:
+## --------------
+##              - added help target
+##              - removed target for timing analysis
+##              - added target project for initial creation of a quartus project
+##              - modified target all to compile
+##              - modified target clean to remove quartus project files *.qpf *.qfs
+##              - added target prog to configure a programmable device
+##              - added target quartus to start quartus graphical user interface
+## ----------------------------------------------------------------------------
+## Revisions:
+## ----------
+## $Id:$
+## ----------------------------------------------------------------------------

pnr/de1_mux2to1/de1_mux2to1_pins.tcl

+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_R20 -to LEDR
+# ----------------------------------------------------------------------------

pnr/de1_mux2to1/de1_mux2to1_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : de1_mux2to1
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: test the module add1 on a DE1 prototype board
+--              connecting device under test (DUT) add1
+--              to input/output signals of the DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_mux2to1 IS
+  PORT (
+    SW   : IN  std_ulogic_vector(2 DOWNTO 0);  -- Toggle Switch[2:0]
+    LEDR : OUT std_ulogic   -- LED Red[0]  
+    );
+END de1_mux2to1;
+
+ARCHITECTURE structure OF de1_mux2to1 IS
+
+  COMPONENT mux2to1
+    PORT (
+      a_i   : IN  std_ulogic;
+      b_i   : IN  std_ulogic;
+      sel_i : IN  std_ulogic;
+      y_o   : OUT std_ulogic);
+  END COMPONENT;
+
+BEGIN
+
+  -- connecting device under test with peripheral elements
+  DUT : mux2to1
+    PORT MAP (
+      a_i   => SW(0),
+      b_i   => SW(1),
+      sel_i => SW(2),
+      y_o   => LEDR);
+  
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------

pnr/de1_mux2to1/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: see end of file
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+# 
+# Prerequisite: - mandatory design directory structure (see end of file)
+#               - scripts/quartus_project_settings.tcl
+#               - scripts/de1_$(PROJECT)_pins.tcl
+#
+# - modify and copy it to pnr/de1_(PROJECT)/makefile
+# - specify the name of the design (PROJECT)
+# - and the list of source files used (SOURCE_FILES)
+###################################################################
+SIM_PROJECT_NAME = mux2to1
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+./$(PROJECT)_structure.vhd
+
+include ../makefile
+
+

pnr/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: see end of file
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Main Targets
+#
+###################################################################
+
+help:
+	@echo '"make" does intentionally nothing. Type:'
+	@echo '  "make qproject" to create a new quartus project'
+	@echo '  "make compile" to process through all design steps: map, fit, asm'
+	@echo '  "make prog" to configure programmable device'
+	@echo '  "make quartus" to start quartus graphical user interface'
+	@echo '  "make clean" to remove all generated files'
+
+qproject: flowsummary.log
+
+flowsummary.log: $(SOURCE_FILES)  
+	# assign VHDL design files
+	rm -rf quartus_vhdl_source_files.tcl
+	for source_file in $(SOURCE_FILES); do \
+		echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \
+	done
+	# create and compile quartus project
+	quartus_sh -t ../../scripts/quartus_project_settings.tcl -projectname $(PROJECT)
+
+clean:
+	rm -rf *.rpt *.chg *.log quartus_vhdl_source_files.tcl *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary $(PROJECT).*
+
+prog: flowsummary.log
+	quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).sof"
+
+quartus: flowsummary.log
+	# create quartus project
+	quartus $(PROJECT).qpf &
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       de1_mux2to1_structure.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       
+## +---pnr
+## |   +---de1_mux2to1
+## |           makefile
+## |           de1_mux2to1.qpf
+## |           de1_mux2to1.qpf
+## |
+## +---scripts
+## |       quartus_project_settings.tcl
+## |       makefile.quartus_template
+## |       makefile.modelsim_template
+## |       de1_mux2to1_pins.tcl
+## |       modelsim_project_settings.tcl
+## |       modelsim.ini
+## |       de1_pin_assignments_minimumio.csv
+## |       de1_pin_assignments_minimumio.tcl
+## |       
+## \---sim
+##     +---mux2to1
+##             makefile
+##             mux2to1.mpf
+##             modelsim.ini
+## 
+## ----------------------------------------------------------------------------
+## Modifications: makefile template from Altera Quartus scripting modified:
+## --------------
+##              - added help target
+##              - removed target for timing analysis
+##              - added target project for initial creation of a quartus project
+##              - modified target all to compile
+##              - modified target clean to remove quartus project files *.qpf *.qfs
+##              - added target prog to configure a programmable device
+##              - added target quartus to start quartus graphical user interface
+## ----------------------------------------------------------------------------
+## Revisions:
+## ----------
+## $Id:$
+## ----------------------------------------------------------------------------

scripts/de1_binto7segment_pins.tcl

+# assign pin locations to an existing quartus project
+# expects project name as command line parameter 
+# e.g.
+# quartus_sh -t de1_mux2to1_pins.tcl -projectname de1_mux2to1
+#
+
+package require cmdline
+
+set parameters {
+    {projectname.arg ""   "Project Name"}
+}
+array set arg [::cmdline::getoptions argv $parameters]
+
+if {[project_exists $arg(projectname)]} {
+    project_open $arg(projectname)
+	# ----------------------------------------------------------------------------
+	# Pin Assignments
+	set_location_assignment PIN_L22 -to SW[0]
+	set_location_assignment PIN_L21 -to SW[1]
+	set_location_assignment PIN_M22 -to SW[2]
+	set_location_assignment PIN_V12 -to SW[3]
+	set_location_assignment PIN_R20 -to LEDR[0]
+	set_location_assignment PIN_R19 -to LEDR[1]
+	set_location_assignment PIN_U19 -to LEDR[2]
+	set_location_assignment PIN_Y19 -to LEDR[3]
+	set_location_assignment PIN_J2 -to HEX0[0]
+	set_location_assignment PIN_J1 -to HEX0[1]
+	set_location_assignment PIN_H2 -to HEX0[2]
+	set_location_assignment PIN_H1 -to HEX0[3]
+	set_location_assignment PIN_F2 -to HEX0[4]
+	set_location_assignment PIN_F1 -to HEX0[5]
+	set_location_assignment PIN_E2 -to HEX0[6]
+	# ----------------------------------------------------------------------------
+	# Close project
+	project_close
+
+} else {
+
+	puts "Project Name not specified !"
+	exit 1
+}

scripts/de1_pin_assignments_minimumio.csv

+To,Location
+CLOCK_27[0],PIN_D12
+CLOCK_27[1],PIN_E12
+CLOCK_24[0],PIN_B12
+CLOCK_24[1],PIN_A12
+CLOCK_50,PIN_L1
+EXT_CLOCK,PIN_M21
+KEY[0],PIN_R22
+KEY[1],PIN_R21
+KEY[2],PIN_T22
+KEY[3],PIN_T21
+SW[0],PIN_L22
+SW[1],PIN_L21
+SW[2],PIN_M22
+SW[3],PIN_V12
+SW[4],PIN_W12
+SW[5],PIN_U12
+SW[6],PIN_U11
+SW[7],PIN_M2
+SW[8],PIN_M1
+SW[9],PIN_L2
+LEDR[0],PIN_R20
+LEDR[1],PIN_R19
+LEDR[2],PIN_U19
+LEDR[3],PIN_Y19
+LEDR[4],PIN_T18
+LEDR[5],PIN_V19
+LEDR[6],PIN_Y18
+LEDR[7],PIN_U18
+LEDR[8],PIN_R18
+LEDR[9],PIN_R17
+LEDG[0],PIN_U22
+LEDG[1],PIN_U21
+LEDG[2],PIN_V22
+LEDG[3],PIN_V21
+LEDG[4],PIN_W22
+LEDG[5],PIN_W21
+LEDG[6],PIN_Y22
+LEDG[7],PIN_Y21
+HEX0[0],PIN_J2
+HEX0[1],PIN_J1
+HEX0[2],PIN_H2
+HEX0[3],PIN_H1
+HEX0[4],PIN_F2
+HEX0[5],PIN_F1
+HEX0[6],PIN_E2
+HEX1[0],PIN_E1
+HEX1[1],PIN_H6
+HEX1[2],PIN_H5
+HEX1[3],PIN_H4
+HEX1[4],PIN_G3
+HEX1[5],PIN_D2
+HEX1[6],PIN_D1
+HEX2[0],PIN_G5
+HEX2[1],PIN_G6
+HEX2[2],PIN_C2
+HEX2[3],PIN_C1
+HEX2[4],PIN_E3
+HEX2[5],PIN_E4
+HEX2[6],PIN_D3
+HEX3[0],PIN_F4
+HEX3[1],PIN_D5
+HEX3[2],PIN_D6
+HEX3[3],PIN_J4
+HEX3[4],PIN_L8
+HEX3[5],PIN_F3
+HEX3[6],PIN_D4
+GPI_0[0],PIN_A13
+GPI_0[1],PIN_B13
+GPI_0[2],PIN_A14
+GPI_0[3],PIN_B14
+GPI_0[4],PIN_A15
+GPI_0[5],PIN_B15
+GPI_0[6],PIN_A16
+GPI_0[7],PIN_B16
+GPI_0[8],PIN_A17
+GPI_0[9],PIN_B17
+GPI_0[10],PIN_A18
+GPI_0[11],PIN_B18
+GPI_0[12],PIN_A19
+GPI_0[13],PIN_B19
+GPI_0[14],PIN_A20
+GPI_0[15],PIN_B20
+GPI_0[16],PIN_C21
+GPI_0[17],PIN_C22
+GPI_0[18],PIN_D21
+GPI_0[19],PIN_D22
+GPI_0[20],PIN_E21
+GPI_0[21],PIN_E22
+GPI_0[22],PIN_F21
+GPI_0[23],PIN_F22
+GPI_0[24],PIN_G21
+GPI_0[25],PIN_G22
+GPI_0[26],PIN_J21
+GPI_0[27],PIN_J22
+GPI_0[28],PIN_K21
+GPI_0[29],PIN_K22
+GPI_0[30],PIN_J19
+GPI_0[31],PIN_J20
+GPI_0[32],PIN_J18
+GPI_0[33],PIN_K20
+GPI_0[34],PIN_L19
+GPI_0[35],PIN_L18
+GPI_1[0],PIN_H12
+GPI_1[1],PIN_H13
+GPI_1[2],PIN_H14
+GPI_1[3],PIN_G15
+GPI_1[4],PIN_E14
+GPI_1[5],PIN_E15
+GPI_1[6],PIN_F15
+GPI_1[7],PIN_G16
+GPI_1[8],PIN_F12
+GPI_1[9],PIN_F13
+GPI_1[10],PIN_C14
+GPI_1[11],PIN_D14
+GPI_1[12],PIN_D15
+GPI_1[13],PIN_D16
+GPI_1[14],PIN_C17
+GPI_1[15],PIN_C18
+GPI_1[16],PIN_C19
+GPI_1[17],PIN_C20
+GPI_1[18],PIN_D19
+GPI_1[19],PIN_D20
+GPI_1[20],PIN_E20
+GPI_1[21],PIN_F20
+GPI_1[22],PIN_E19
+GPI_1[23],PIN_E18
+GPI_1[24],PIN_G20
+GPI_1[25],PIN_G18
+GPI_1[26],PIN_G17
+GPI_1[27],PIN_H17
+GPI_1[28],PIN_J15
+GPI_1[29],PIN_H18
+GPI_1[30],PIN_N22
+GPI_1[31],PIN_N21
+GPI_1[32],PIN_P15
+GPI_1[33],PIN_N15
+GPI_1[34],PIN_P17
+GPI_1[35],PIN_P18
+GPO_0[0],PIN_A13
+GPO_0[1],PIN_B13
+GPO_0[2],PIN_A14
+GPO_0[3],PIN_B14
+GPO_0[4],PIN_A15
+GPO_0[5],PIN_B15
+GPO_0[6],PIN_A16
+GPO_0[7],PIN_B16
+GPO_0[8],PIN_A17
+GPO_0[9],PIN_B17
+GPO_0[10],PIN_A18
+GPO_0[11],PIN_B18
+GPO_0[12],PIN_A19
+GPO_0[13],PIN_B19
+GPO_0[14],PIN_A20
+GPO_0[15],PIN_B20
+GPO_0[16],PIN_C21
+GPO_0[17],PIN_C22
+GPO_0[18],PIN_D21
+GPO_0[19],PIN_D22
+GPO_0[20],PIN_E21
+GPO_0[21],PIN_E22
+GPO_0[22],PIN_F21
+GPO_0[23],PIN_F22
+GPO_0[24],PIN_G21
+GPO_0[25],PIN_G22
+GPO_0[26],PIN_J21
+GPO_0[27],PIN_J22
+GPO_0[28],PIN_K21
+GPO_0[29],PIN_K22
+GPO_0[30],PIN_J19
+GPO_0[31],PIN_J20
+GPO_0[32],PIN_J18
+GPO_0[33],PIN_K20
+GPO_0[34],PIN_L19
+GPO_0[35],PIN_L18
+GPO_1[0],PIN_H12
+GPO_1[1],PIN_H13
+GPO_1[2],PIN_H14
+GPO_1[3],PIN_G15
+GPO_1[4],PIN_E14
+GPO_1[5],PIN_E15
+GPO_1[6],PIN_F15
+GPO_1[7],PIN_G16
+GPO_1[8],PIN_F12
+GPO_1[9],PIN_F13
+GPO_1[10],PIN_C14
+GPO_1[11],PIN_D14
+GPO_1[12],PIN_D15
+GPO_1[13],PIN_D16
+GPO_1[14],PIN_C17
+GPO_1[15],PIN_C18
+GPO_1[16],PIN_C19
+GPO_1[17],PIN_C20
+GPO_1[18],PIN_D19
+GPO_1[19],PIN_D20
+GPO_1[20],PIN_E20
+GPO_1[21],PIN_F20
+GPO_1[22],PIN_E19
+GPO_1[23],PIN_E18
+GPO_1[24],PIN_G20
+GPO_1[25],PIN_G18
+GPO_1[26],PIN_G17
+GPO_1[27],PIN_H17
+GPO_1[28],PIN_J15
+GPO_1[29],PIN_H18
+GPO_1[30],PIN_N22
+GPO_1[31],PIN_N21
+GPO_1[32],PIN_P15
+GPO_1[33],PIN_N15
+GPO_1[34],PIN_P17
+GPO_1[35],PIN_P18
+GPIO_0[0],PIN_A13
+GPIO_0[1],PIN_B13
+GPIO_0[2],PIN_A14
+GPIO_0[3],PIN_B14
+GPIO_0[4],PIN_A15
+GPIO_0[5],PIN_B15
+GPIO_0[6],PIN_A16
+GPIO_0[7],PIN_B16
+GPIO_0[8],PIN_A17
+GPIO_0[9],PIN_B17
+GPIO_0[10],PIN_A18
+GPIO_0[11],PIN_B18
+GPIO_0[12],PIN_A19
+GPIO_0[13],PIN_B19
+GPIO_0[14],PIN_A20
+GPIO_0[15],PIN_B20
+GPIO_0[16],PIN_C21
+GPIO_0[17],PIN_C22
+GPIO_0[18],PIN_D21
+GPIO_0[19],PIN_D22
+GPIO_0[20],PIN_E21