removed sim in pnr makefiles for ledsw, ledcomb and cntsw

For the first simple labs the simulator seems to be useless
because the function is so simple.

pnr/ledcntsw/makefile

-## ----------------------------------------------------------------------------
-## Script     : makefile
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber, Friedrich Beckmann
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: This makefile allows automating design flow with Quartus,
-##              it is based on a design directory structure described in 
-##              ../makefile
-## ----------------------------------------------------------------------------
+# The PROJECT variable must match the
+# toplevel VHDL entity name
+# and should match the directory name in the pnr directory
 
-###################################################################
-# Project Configuration: 
-#
-# - assign variable SIM_PROJECT_NAME with the top level project name
-# - add additional VHDL sources to SOURCE_FILES, if necessary
-#
-# Prerequisite: 
-#   - mandatory design directory structure (see end of file)
-#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
-###################################################################
+PROJECT = ledcntsw
 
-SIM_PROJECT_NAME = ledcntsw
-PROJECT = $(SIM_PROJECT_NAME)
-
-# Here the VHDL files for synthesis are defined. 
-include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
-
-# Add the toplevel fpga vhdl file
-SOURCE_FILES = $(SYN_SOURCE_FILES) 
+SOURCE_FILES = \
+../../src/ledcntsw_rtl.vhd \
+../../src/cntones_rtl.vhd
 
 include ../makefile
-
-

pnr/ledcomb/makefile

-## ----------------------------------------------------------------------------
-## Script     : makefile
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber, Friedrich Beckmann
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: This makefile allows automating design flow with Quartus,
-##              it is based on a design directory structure described in 
-##              ../makefile
-## ----------------------------------------------------------------------------
+# The PROJECT variable must match the
+# toplevel VHDL entity name (here: entity ledcomb)
+# and should match the directory name in the pnr directory
 
-###################################################################
-# Project Configuration: 
-#
-# - assign variable SIM_PROJECT_NAME with the top level project name
-# - add additional VHDL sources to SOURCE_FILES, if necessary
-#
-# Prerequisite: 
-#   - mandatory design directory structure (see end of file)
-#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
-###################################################################
+PROJECT = ledcomb
 
-SIM_PROJECT_NAME = ledcomb
-PROJECT = $(SIM_PROJECT_NAME)
-
-# Here the VHDL files for synthesis are defined. 
-include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
-
-# Add the toplevel fpga vhdl file
-SOURCE_FILES = $(SYN_SOURCE_FILES) 
+# Define the list of VHDL files for this project
+SOURCE_FILES = ../../src/ledcomb_rtl.vhd
 
 include ../makefile
-
-

pnr/ledsw-make/makefile

-## ----------------------------------------------------------------------------
-## Script     : makefile
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber, Friedrich Beckmann
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: This makefile allows automating design flow with Quartus,
-##              it is based on a design directory structure described in 
-##              ../makefile
-## ----------------------------------------------------------------------------
+# The PROJECT variable must match the
+# toplevel VHDL entity name (here: entity ledsw)
 
-###################################################################
-# Project Configuration: 
-#
-# - assign variable SIM_PROJECT_NAME with the top level project name
-# - add additional VHDL sources to SOURCE_FILES, if necessary
-#
-# Prerequisite: 
-#   - mandatory design directory structure (see end of file)
-#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
-###################################################################
+PROJECT = ledsw
 
-SIM_PROJECT_NAME = ledsw
-PROJECT = $(SIM_PROJECT_NAME)
-
-# Here the VHDL files for synthesis are defined. 
-include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
-
-# Add the toplevel fpga vhdl file
-SOURCE_FILES = $(SYN_SOURCE_FILES) 
+# All VHDL Files for the project
+SOURCE_FILES = ../../src/ledsw_rtl.vhd
 
 include ../makefile
-
-