Commit 9cd7500a authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

removed sim in pnr makefiles for ledsw, ledcomb and cntsw

For the first simple labs the simulator seems to be useless
because the function is so simple.
parent 8dc8e16a
## ---------------------------------------------------------------------------- # The PROJECT variable must match the
## Script : makefile # toplevel VHDL entity name
## ---------------------------------------------------------------------------- # and should match the directory name in the pnr directory
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
################################################################### PROJECT = ledcntsw
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = ledcntsw SOURCE_FILES = \
PROJECT = $(SIM_PROJECT_NAME) ../../src/ledcntsw_rtl.vhd \
../../src/cntones_rtl.vhd
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile include ../makefile
## ---------------------------------------------------------------------------- # The PROJECT variable must match the
## Script : makefile # toplevel VHDL entity name (here: entity ledcomb)
## ---------------------------------------------------------------------------- # and should match the directory name in the pnr directory
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
################################################################### PROJECT = ledcomb
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = ledcomb # Define the list of VHDL files for this project
PROJECT = $(SIM_PROJECT_NAME) SOURCE_FILES = ../../src/ledcomb_rtl.vhd
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile include ../makefile
## ---------------------------------------------------------------------------- # The PROJECT variable must match the
## Script : makefile # toplevel VHDL entity name (here: entity ledsw)
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
################################################################### PROJECT = ledsw
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = ledsw # All VHDL Files for the project
PROJECT = $(SIM_PROJECT_NAME) SOURCE_FILES = ../../src/ledsw_rtl.vhd
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile include ../makefile
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment