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Friedrich Beckmann
digitaltechnikpraktikum
Commits
a89f837b
Commit
a89f837b
authored
Jul 15, 2013
by
Johann Faerber
Browse files
deleted .vhd files in sim and pnr directories
parent
4591dd18
Changes
7
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pnr/de1_add1/de1_add1_structure.vhd
deleted
100644 → 0
View file @
4591dd18
-------------------------------------------------------------------------------
-- Module : de1_add1
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: test the module add1 on a DE1 prototype board
-- connecting device under test (DUT) add1
-- to input/output signals of the DE1 prototype board
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
de1_add1
IS
PORT
(
SW
:
IN
std_ulogic_vector
(
2
DOWNTO
0
);
-- Toggle Switch[2:0]
LEDR
:
OUT
std_ulogic_vector
(
1
DOWNTO
0
)
-- LED Red[1:0]
);
END
de1_add1
;
ARCHITECTURE
structure
OF
de1_add1
IS
COMPONENT
add1
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
ci_i
:
IN
std_ulogic
;
sum_o
:
OUT
std_ulogic
;
co_o
:
OUT
std_ulogic
);
END
COMPONENT
;
BEGIN
-- connecting device under test with peripheral elements
DUT
:
add1
PORT
MAP
(
a_i
=>
SW
(
0
),
b_i
=>
SW
(
1
),
ci_i
=>
SW
(
2
),
sum_o
=>
LEDR
(
0
),
co_o
=>
LEDR
(
1
)
);
END
structure
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
pnr/de1_binto7segment/de1_binto7segment_structure.vhd
deleted
100755 → 0
View file @
4591dd18
-------------------------------------------------------------------------------
-- Module : de1_binto7segment
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: test the module binto7segment on a DE1 prototype board
-- connecting device under test (DUT) binto7segment
-- to input/output signals of the DE1 prototype board
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
de1_binto7segment
IS
PORT
(
SW
:
IN
std_ulogic_vector
(
3
DOWNTO
0
);
-- Toggle Switch[3:0]
LEDR
:
OUT
std_ulogic_vector
(
3
DOWNTO
0
);
-- LED Red[3:0]
HEX0
:
OUT
std_ulogic_vector
(
6
DOWNTO
0
)
-- Seven Segment Digit 0
);
END
de1_binto7segment
;
ARCHITECTURE
structure
OF
de1_binto7segment
IS
COMPONENT
binto7segment
PORT
(
bin_i
:
IN
std_ulogic_vector
(
3
DOWNTO
0
);
segments_o
:
OUT
std_ulogic_vector
(
6
DOWNTO
0
));
END
COMPONENT
;
BEGIN
-- connecting device under test with peripheral elements
DUT
:
binto7segment
PORT
MAP
(
bin_i
=>
SW
,
segments_o
=>
HEX0
);
-- connect switches to red LEDs
LEDR
<=
SW
;
END
structure
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
pnr/de1_mux2to1/de1_mux2to1_structure.vhd
deleted
100755 → 0
View file @
4591dd18
-------------------------------------------------------------------------------
-- Module : de1_mux2to1
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: test the module add1 on a DE1 prototype board
-- connecting device under test (DUT) add1
-- to input/output signals of the DE1 prototype board
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
de1_mux2to1
IS
PORT
(
SW
:
IN
std_ulogic_vector
(
2
DOWNTO
0
);
-- Toggle Switch[2:0]
LEDR
:
OUT
std_ulogic
-- LED Red[0]
);
END
de1_mux2to1
;
ARCHITECTURE
structure
OF
de1_mux2to1
IS
COMPONENT
mux2to1
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
sel_i
:
IN
std_ulogic
;
y_o
:
OUT
std_ulogic
);
END
COMPONENT
;
BEGIN
-- connecting device under test with peripheral elements
DUT
:
mux2to1
PORT
MAP
(
a_i
=>
SW
(
0
),
b_i
=>
SW
(
1
),
sel_i
=>
SW
(
2
),
y_o
=>
LEDR
);
END
structure
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
sim/add1/t_add1.vhd
deleted
100644 → 0
View file @
4591dd18
-------------------------------------------------------------------------------
-- Module : t_add1
-------------------------------------------------------------------------------
-- Author : <haf@fh-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2011 <haf@fh-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "add1"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
ALL
;
-------------------------------------------------------------------------------
ENTITY
t_add1
IS
END
t_add1
;
-------------------------------------------------------------------------------
ARCHITECTURE
tbench
OF
t_add1
IS
COMPONENT
add1
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
ci_i
:
IN
std_ulogic
;
sum_o
:
OUT
std_ulogic
;
co_o
:
OUT
std_ulogic
);
END
COMPONENT
;
-- definition of a clock period
CONSTANT
period
:
time
:
=
10
ns
;
-- component ports
SIGNAL
a_i
:
std_ulogic
;
SIGNAL
b_i
:
std_ulogic
;
SIGNAL
ci_i
:
std_ulogic
;
SIGNAL
sum_o
:
std_ulogic
;
SIGNAL
co_o
:
std_ulogic
;
BEGIN
-- tbench
-- component instantiation
MUV
:
add1
PORT
MAP
(
a_i
=>
a_i
,
b_i
=>
b_i
,
ci_i
=>
ci_i
,
sum_o
=>
sum_o
,
co_o
=>
co_o
);
stimuli_p
:
PROCESS
-- purpose: apply stimuli to input signals of module under test
PROCEDURE
apply_stimuli
(
CONSTANT
ci_stim
,
b_stim
,
a_stim
:
IN
std_ulogic
)
IS
BEGIN
-- apply_stimuli
a_i
<=
a_stim
;
b_i
<=
b_stim
;
ci_i
<=
ci_stim
;
WAIT
FOR
period
;
END
PROCEDURE
apply_stimuli
;
BEGIN
a_i
<=
'0'
;
-- set a value to input a_i
b_i
<=
'0'
;
-- set a value to input b_i
ci_i
<=
'0'
;
-- set a value to input ci_i
WAIT
FOR
period
;
-- values are assigned here
a_i
<=
'1'
;
-- change value of a_i
WAIT
FOR
period
;
a_i
<=
'0'
;
-- change value of a_i
b_i
<=
'1'
;
-- change value of b_i
WAIT
FOR
period
;
-- alternatively, a local procedure can be used to assign input values:
-- apply_stimuli('0', '0', '0');
-- apply_stimuli('0', '0', '1');
-- apply_stimuli('0', '1', '0');
apply_stimuli
(
'0'
,
'1'
,
'1'
);
apply_stimuli
(
'1'
,
'0'
,
'0'
);
apply_stimuli
(
'1'
,
'0'
,
'1'
);
apply_stimuli
(
'1'
,
'1'
,
'0'
);
apply_stimuli
(
'1'
,
'1'
,
'1'
);
WAIT
;
END
PROCESS
;
END
tbench
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
sim/binto7segment/binto7segment_stimuli.vhd
deleted
100755 → 0
View file @
4591dd18
-------------------------------------------------------------------------------
-- Module : binto7segment_stimuli
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: stimuli for verification of binary-to-7-segment decoder
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
binto7segment_stimuli
IS
PORT
(
stimuli_o
:
OUT
std_ulogic_vector
(
3
DOWNTO
0
)
);
END
binto7segment_stimuli
;
ARCHITECTURE
stimuli
OF
binto7segment_stimuli
IS
-- definition of a clock period
CONSTANT
period
:
time
:
=
10
ns
;
BEGIN
stimuli_p
:
PROCESS
BEGIN
stimuli_o
<=
"0000"
;
WAIT
FOR
period
;
stimuli_o
<=
"0001"
;
WAIT
FOR
period
;
stimuli_o
<=
"0010"
;
WAIT
FOR
period
;
stimuli_o
<=
"0011"
;
WAIT
FOR
period
;
stimuli_o
<=
"0100"
;
WAIT
FOR
period
;
stimuli_o
<=
"0101"
;
WAIT
FOR
period
;
stimuli_o
<=
"0110"
;
WAIT
FOR
period
;
stimuli_o
<=
"0111"
;
WAIT
FOR
period
;
stimuli_o
<=
"1000"
;
WAIT
FOR
period
;
stimuli_o
<=
"1001"
;
WAIT
FOR
period
;
stimuli_o
<=
"1010"
;
WAIT
FOR
period
;
stimuli_o
<=
"1011"
;
WAIT
FOR
period
;
stimuli_o
<=
"1100"
;
WAIT
FOR
period
;
stimuli_o
<=
"1101"
;
WAIT
FOR
period
;
stimuli_o
<=
"1110"
;
WAIT
FOR
period
;
stimuli_o
<=
"1111"
;
WAIT
FOR
period
;
WAIT
;
END
PROCESS
;
END
stimuli
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
sim/binto7segment/t_binto7segment.vhd
deleted
100755 → 0
View file @
4591dd18
-------------------------------------------------------------------------------
-- Module : t_binto7segment
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Testbench for design "binto7segment"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
ALL
;
-------------------------------------------------------------------------------
ENTITY
t_binto7segment
IS
END
t_binto7segment
;
-------------------------------------------------------------------------------
ARCHITECTURE
tbench
OF
t_binto7segment
IS
COMPONENT
binto7segment_stimuli
PORT
(
stimuli_o
:
OUT
std_ulogic_vector
(
3
DOWNTO
0
));
END
COMPONENT
;
COMPONENT
binto7segment
PORT
(
bin_i
:
IN
std_ulogic_vector
(
3
DOWNTO
0
);
segments_o
:
OUT
std_ulogic_vector
(
6
DOWNTO
0
));
END
COMPONENT
;
-- stimuli generator ports
SIGNAL
stimuli_o
:
std_ulogic_vector
(
3
DOWNTO
0
);
-- component ports
-- SIGNAL bin_i : std_ulogic_vector(3 DOWNTO 0);
SIGNAL
segments_o
:
std_ulogic_vector
(
6
DOWNTO
0
);
BEGIN
-- tbench
-- component instantiation
MUV
:
binto7segment
PORT
MAP
(
bin_i
=>
stimuli_o
,
segments_o
=>
segments_o
);
stimuli
:
binto7segment_stimuli
PORT
MAP
(
stimuli_o
=>
stimuli_o
);
END
tbench
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
sim/mux2to1/t_mux2to1.vhd
deleted
100755 → 0
View file @
4591dd18
-------------------------------------------------------------------------------
-- Module : t_mux2to1
-------------------------------------------------------------------------------
-- Author : <haf@fh-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2011 <haf@fh-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "mux2to1"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
ieee
;
USE
ieee
.
std_logic_1164
.
ALL
;
-------------------------------------------------------------------------------
ENTITY
t_mux2to1
IS
END
t_mux2to1
;
-------------------------------------------------------------------------------
ARCHITECTURE
tbench
OF
t_mux2to1
IS
COMPONENT
mux2to1
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
sel_i
:
IN
std_ulogic
;
y_o
:
OUT
std_ulogic
);
END
COMPONENT
;
-- definition of a clock period
CONSTANT
period
:
time
:
=
10
ns
;
-- component ports
SIGNAL
a_i
:
std_ulogic
;
SIGNAL
b_i
:
std_ulogic
;
SIGNAL
sel_i
:
std_ulogic
;
SIGNAL
y_o
:
std_ulogic
;
BEGIN
-- tbench
-- component instantiation
MUV
:
mux2to1
PORT
MAP
(
a_i
=>
a_i
,
b_i
=>
b_i
,
sel_i
=>
sel_i
,
y_o
=>
y_o
);
stimuli_p
:
PROCESS
-- purpose: apply stimuli to input signals of module under test
PROCEDURE
apply_stimuli
(
CONSTANT
sel_stim
,
b_stim
,
a_stim
:
IN
std_ulogic
)
IS
BEGIN
-- apply_stimuli
a_i
<=
a_stim
;
b_i
<=
b_stim
;
sel_i
<=
sel_stim
;
WAIT
FOR
period
;
END
PROCEDURE
apply_stimuli
;
BEGIN
a_i
<=
'0'
;
-- set a value to input a_i
b_i
<=
'0'
;
-- set a value to input b_i
sel_i
<=
'0'
;
-- set a value to input ci_i
WAIT
FOR
period
;
-- values are assigned here
a_i
<=
'1'
;
-- change value of a_i
WAIT
FOR
period
;
a_i
<=
'0'
;
-- change value of a_i
b_i
<=
'1'
;
-- change value of b_i
WAIT
FOR
period
;
-- alternatively, a local procedure can be used to assign input values:
-- apply_stimuli('0', '0', '0');
-- apply_stimuli('0', '0', '1');
-- apply_stimuli('0', '1', '0');
apply_stimuli
(
'0'
,
'1'
,
'1'
);
apply_stimuli
(
'1'
,
'0'
,
'0'
);
apply_stimuli
(
'1'
,
'0'
,
'1'
);
apply_stimuli
(
'1'
,
'1'
,
'0'
);
apply_stimuli
(
'1'
,
'1'
,
'1'
);
WAIT
;
END
PROCESS
;
END
tbench
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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