Commit b65298e9 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

added blnkauto

parent 823df493
# Pin Configuration
set_location_assignment PIN_L22 -to SW0
set_location_assignment PIN_R22 -to KEY0
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_R17 -to LEDR[9]
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
SIM_PROJECT_NAME = de1_blnkauto
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
PROJECT = de1_blnkauto
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/de1_blnkauto_rtl.vhd \
../../src/blnkctr_rtl.vhd \
../../src/cntblnk_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity blnkctr is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
schalter_i : in std_ulogic;
ld_short_o : out std_ulogic;
ld_long_o : out std_ulogic;
done_i : in std_ulogic;
led_o : out std_ulogic_vector(9 downto 0));
end entity;
architecture rtl of blnkctr is
begin
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Loadable downcounter which stops when cnt is 0
-- The done_o output is 1, when cnt is 0;
entity cntblnk is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
ld_short_i : in std_ulogic;
ld_long_i : in std_ulogic;
done_o : out std_ulogic);
end entity;
architecture rtl of cntblnk is
begin
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity de1_blnkauto is
port ( CLOCK_50 : in std_ulogic;
SW0 : in std_ulogic;
KEY0 : in std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end entity;
architecture rtl of de1_blnkauto is
component blnkctr is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
schalter_i : in std_ulogic;
ld_short_o : out std_ulogic;
ld_long_o : out std_ulogic;
done_i : in std_ulogic;
led_o : out std_ulogic_vector(9 downto 0));
end component;
component cntblnk is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
ld_short_i : in std_ulogic;
ld_long_i : in std_ulogic;
done_o : out std_ulogic);
end component;
begin
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity t_de1_blnkauto is
end;
architecture tbench of t_de1_blnkauto is
component de1_blnkauto is
port ( CLOCK_50 : in std_ulogic;
SW0 : in std_ulogic;
KEY0 : in std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end component;
signal redleds : std_ulogic_vector(9 downto 0);
signal clk, rst_n : std_ulogic;
signal simstop : boolean := false;
signal schalter : std_ulogic;
begin
de1_blnkauto_i0 : de1_blnkauto
port map (
CLOCK_50 => clk,
SW0 => schalter,
KEY0 => rst_n,
LEDR => redleds);
rst_n <= '1', '0' after 20 ns, '1' after 40 ns;
clk_p : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if simstop then
wait;
end if;
end process clk_p;
-- This is the process where the switches are switched.
schalter_p : process
begin
schalter <= '0';
wait until rising_edge(rst_n);
wait until falling_edge(clk);
schalter <= '1';
wait for 300 ns;
schalter <= '0';
wait for 300 ns;
schalter <= '1';
wait for 300 ns;
schalter <= '0';
wait for 400 ns;
simstop <= true;
wait;
end process schalter_p;
end; -- architecture
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment