Commit bd12eab6 authored by Johann Faerber's avatar Johann Faerber
Browse files

added design binto7segment

parent 9bd5231d
......@@ -18,142 +18,16 @@
# - specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
###################################################################
PROTOTYPE = de1
PROJECT = de1_binto7segment
SOURCE_FILES = \
../../src/binto7segment_stimuli.vhd \
../../src/binto7segment_truthtable.vhd \
../../src/$(PROJECT)_structure.vhd
ASSIGNMENT_FILES = $(PROJECT).qpf $(PROJECT).qsf
SIM_PROJECT_NAME = binto7segment
PROJECT = de1_$(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
###################################################################
# Main Targets
#
###################################################################
help:
@echo '"make" does intentionally nothing. Type:'
@echo ' "make clean" to remove all generated files'
@echo ' "make project" to create a new quartus project'
@echo ' "make compile" to process through all design steps: map, fit, asm'
@echo ' "make prog" to configure programmable device'
@echo ' "make quartus" to start quartus graphical user interface'
compile: smart.log $(PROJECT).asm.rpt
project:
# create quartus project
quartus_sh -t ../../scripts/quartus_project_settings.tcl -projectname $(PROJECT)
# assign VHDL design files
for source_file in $(SOURCE_FILES); do \
quartus_sh --set VHDL_FILE=$$source_file $(PROJECT); \
done
# assign pins
$ if [ -f ../../scripts/$(PROJECT)_pins.tcl ]; then quartus_sh -t ../../scripts/$(PROJECT)_pins.tcl -projectname $(PROJECT); fi
clean:
rm -rf *.rpt *.chg smart.log *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary
map: smart.log $(PROJECT).map.rpt
fit: smart.log $(PROJECT).fit.rpt
asm: smart.log $(PROJECT).asm.rpt
smart: smart.log
prog:
quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).sof"
quartus:
# create quartus project
quartus $(PROJECT).qpf &
###################################################################
# Target implementations
###################################################################
STAMP = echo done >
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./$(PROJECT)_structure.vhd
$(PROJECT).map.rpt: map.chg $(SOURCE_FILES)
quartus_map $(PROJECT)
$(STAMP) fit.chg
include ../makefile
$(PROJECT).fit.rpt: fit.chg $(PROJECT).map.rpt
quartus_fit $(PROJECT)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
quartus_asm $(ASM_ARGS) $(PROJECT)
smart.log: $(ASSIGNMENT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
###################################################################
# Project initialization
###################################################################
$(ASSIGNMENT_FILES):
quartus_sh --prepare $(PROJECT)
map.chg:
$(STAMP) map.chg
fit.chg:
$(STAMP) fit.chg
asm.chg:
$(STAMP) asm.chg
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | de1_mux2to1_structure.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## |
## +---pnr
## | +---de1_mux2to1
## | makefile
## | de1_mux2to1.qpf
## | de1_mux2to1.qpf
## |
## +---scripts
## | quartus_project_settings.tcl
## | makefile.quartus_template
## | makefile.modelsim_template
## | de1_mux2to1_pins.tcl
## | modelsim_project_settings.tcl
## | modelsim.ini
## | de1_pin_assignments_minimumio.csv
## | de1_pin_assignments_minimumio.tcl
## |
## \---sim
## +---mux2to1
## makefile
## mux2to1.mpf
## modelsim.ini
##
## ----------------------------------------------------------------------------
## Modifications: makefile template from Altera Quartus scripting modified:
## --------------
## - added help target
## - removed target for timing analysis
## - added target project for initial creation of a quartus project
## - modified target all to compile
## - modified target clean to remove quartus project files *.qpf *.qfs
## - added target prog to configure a programmable device
## - added target quartus to start quartus graphical user interface
## ----------------------------------------------------------------------------
## Revisions:
## ----------
## $Id:$
## ----------------------------------------------------------------------------
......@@ -18,93 +18,13 @@
###################################################################
PROJECT = binto7segment
SOURCE_FILES = \
../../src/binto7segment_stimuli.vhd \
../../src/binto7segment_truthtable.vhd \
../../src/de1_binto7segment_structure.vhd \
../../src/t_$(PROJECT).vhd
include ./makefile.sources
###################################################################
# Main Targets
#
###################################################################
help:
@echo '"make" does intentionally nothing. Type:'
@echo ' "make clean" to remove all generated files'
@echo ' "make project" to create a new modelsim project'
@echo ' "make modelsim" to start modelsim with graphical user interface'
@echo ' "make sim" to start modelsim gui with the top testbench of the project'
@echo ' "make compile" to compile all VHDL sources in batch mode'
project :
# create modelsim project
vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); quit -f"
# assign VHDL design files
for source_file in $(SOURCE_FILES); do \
vsim -c -do "project open $(PROJECT); project addfile $$source_file; quit -f" ; \
done
compile:
vsim -c -do "project open $(PROJECT); project calculateorder; quit -f"
modelsim:
vsim -do "project open $(PROJECT); " &
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./binto7segment_stimuli.vhd \
./t_$(PROJECT).vhd
sim:
vsim -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;" &
include ../makefile
clean:
rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | de1_mux2to1_structure.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## |
## +---pnr
## | +---de1_mux2to1
## | makefile
## | de1_mux2to1.qpf
## | de1_mux2to1.qpf
## |
## +---scripts
## | quartus_project_settings.tcl
## | makefile.quartus_template
## | makefile.modelsim_template
## | de1_mux2to1_pins.tcl
## | modelsim_project_settings.tcl
## | modelsim.ini
## | de1_pin_assignments_minimumio.csv
## | de1_pin_assignments_minimumio.tcl
## |
## \---sim
## +---mux2to1
## makefile
## mux2to1.mpf
## modelsim.ini
##
## ----------------------------------------------------------------------------
## Modifications: makefile template from Altera Quartus scripting modified:
## --------------
## - added help target
## - make project to create a new modelsim project
## - make modelsim to start modelsim with graphical user interface
## - make sim to start modelsim gui with the top testbench of the project
## - make compile to compile all VHDL sources in batch mode
## ----------------------------------------------------------------------------
## Revisions:
## ----------
## $Id:$
## ----------------------------------------------------------------------------
......@@ -6,9 +6,9 @@
## ----------------------------------------------------------------------------
## Description: see end of file
## ----------------------------------------------------------------------------
###################################################################
# Main Targets
#
......@@ -21,35 +21,35 @@ help:
@echo ' "make modelsim" to start modelsim with graphical user interface'
@echo ' "make sim" to start modelsim gui with the top testbench of the project'
@echo ' "make clean" to remove all generated files'
mproject : $(PROJECT).mpf
$(PROJECT).mpf : $(SOURCE_FILES)
mproject : $(PROJECT).mpf
$(PROJECT).mpf : $(SOURCE_FILES)
# create modelsim project
# vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); quit -f"
rm -rf ./modelsim_sources.tcl
for source_file in $(SOURCE_FILES); do \
echo project addfile $$source_file >> modelsim_sources.tcl; \
done
vsim -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f"
rm -rf ./modelsim_sources.tcl
for source_file in $(SOURCE_FILES); do \
echo project addfile $$source_file >> modelsim_sources.tcl; \
done
vsim -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f"
# assign VHDL design files
# for source_file in $(SOURCE_FILES); do \
# vsim -c -do "project open $(PROJECT); project addfile $$source_file; quit -f" ; \
# done
compile: ./work/_vmake
./work/_vmake: $(PROJECT).mpf
compile: ./work/_vmake
./work/_vmake: $(PROJECT).mpf
vsim -c -do "project open $(PROJECT); project calculateorder; quit -f"
modelsim: ./work/_vmake
vsim $(PROJECT)
modelsim: ./work/_vmake
vsim -i $(PROJECT) &
sim: ./work/_vmake
vsim -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;"
sim: ./work/_vmake
vsim -i -do "project open $(PROJECT); vsim work.t_$(PROJECT)(tbench); add wave *; run -a;"
clean:
rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work modelsim_sources.tcl
rm -rf *.mpf *.mti *.ini *.wlf wlf* transcript work modelsim_sources.tcl
## ----------------------------------------------------------------------------
## Description:
......
-------------------------------------------------------------------------------
-- Module : binto7segment_stimuli
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: stimuli for verification of binary-to-7-segment decoder
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY binto7segment_stimuli IS
PORT (
stimuli_o : OUT std_ulogic_vector(3 DOWNTO 0)
);
END binto7segment_stimuli;
ARCHITECTURE stimuli OF binto7segment_stimuli IS
-- definition of a clock period
CONSTANT period : time := 10 ns;
BEGIN
stimuli_p : PROCESS
BEGIN
stimuli_o <= "0000";
WAIT FOR period;
stimuli_o <= "0001";
WAIT FOR period;
stimuli_o <= "0010";
WAIT FOR period;
stimuli_o <= "0011";
WAIT FOR period;
stimuli_o <= "0100";
WAIT FOR period;
stimuli_o <= "0101";
WAIT FOR period;
stimuli_o <= "0110";
WAIT FOR period;
stimuli_o <= "0111";
WAIT FOR period;
stimuli_o <= "1000";
WAIT FOR period;
stimuli_o <= "1001";
WAIT FOR period;
stimuli_o <= "1010";
WAIT FOR period;
stimuli_o <= "1011";
WAIT FOR period;
stimuli_o <= "1100";
WAIT FOR period;
stimuli_o <= "1101";
WAIT FOR period;
stimuli_o <= "1110";
WAIT FOR period;
stimuli_o <= "1111";
WAIT FOR period;
WAIT;
END PROCESS;
END stimuli;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : de1_binto7segment
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: test the module binto7segment on a DE1 prototype board
-- connecting device under test (DUT) binto7segment
-- to input/output signals of the DE1 prototype board
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY de1_binto7segment IS
PORT (
SW : IN std_ulogic_vector(3 DOWNTO 0); -- Toggle Switch[3:0]
LEDR : OUT std_ulogic_vector(3 DOWNTO 0); -- LED Red[3:0]
HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0
);
END de1_binto7segment;
ARCHITECTURE structure OF de1_binto7segment IS
COMPONENT binto7segment
PORT (
bin_i : IN std_ulogic_vector(3 DOWNTO 0);
segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
END COMPONENT;
BEGIN
-- connecting device under test with peripheral elements
DUT : binto7segment
PORT MAP (
bin_i => SW,
segments_o => HEX0);
-- connect switches to red LEDs
LEDR <= SW;
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : t_binto7segment
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Testbench for design "binto7segment"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_binto7segment IS
END t_binto7segment;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_binto7segment IS
COMPONENT binto7segment_stimuli
PORT (
stimuli_o : OUT std_ulogic_vector(3 DOWNTO 0));
END COMPONENT;
COMPONENT binto7segment
PORT (
bin_i : IN std_ulogic_vector(3 DOWNTO 0);
segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
END COMPONENT;
-- stimuli generator ports
SIGNAL stimuli_o : std_ulogic_vector(3 DOWNTO 0);
-- component ports
-- SIGNAL bin_i : std_ulogic_vector(3 DOWNTO 0);
SIGNAL segments_o : std_ulogic_vector(6 DOWNTO 0);
BEGIN -- tbench
-- component instantiation
MUV : binto7segment
PORT MAP (
bin_i => stimuli_o,
segments_o => segments_o);
stimuli : binto7segment_stimuli
PORT MAP (
stimuli_o => stimuli_o);
END tbench;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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