Commit c7c075df authored by Johann Faerber's avatar Johann Faerber
Browse files

in sim/makefile

added -modelsimini ../../scripts/modelsim.ini
parent 40fad16a
......@@ -31,7 +31,7 @@ $(PROJECT).mpf : $(SOURCE_FILES)
for source_file in $(SOURCE_FILES); do \
echo project addfile $$source_file >> modelsim_sources.tcl; \
done
vsim -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f"
vsim -modelsimini ../../scripts/modelsim.ini -c -do "project new [pwd] $(PROJECT); source ./modelsim_sources.tcl; quit -f"
# assign VHDL design files
# for source_file in $(SOURCE_FILES); do \
# vsim -c -do "project open $(PROJECT); project addfile $$source_file; quit -f" ; \
......
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