Commit e4819f38 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

added sequence detection with pnr and sim

parent b65298e9
# Pin Configuration
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_R22 -to KEY0
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_R17 -to LEDR[9]
set_location_assignment PIN_H13 -to EXP_PIN2
set_location_assignment PIN_G15 -to EXP_PIN4
set_location_assignment PIN_E15 -to EXP_PIN6
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
SIM_PROJECT_NAME = de1_seq
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
PROJECT = de1_seq
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/de1_seq_rtl.vhd \
../../src/seqgen_rtl.vhd \
../../src/seqdet_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity de1_seq is
port ( CLOCK_50 : in std_ulogic;
SW : in std_ulogic_vector(3 downto 0);
KEY0 : in std_ulogic;
EXP_PIN2 : out std_ulogic;
EXP_PIN4 : out std_ulogic;
EXP_PIN6 : out std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end entity;
architecture rtl of de1_seq is
component seqgen is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
ctrl_i : in std_ulogic_vector(3 downto 0);
ser_o : out std_ulogic);
end component;
component seqdet is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
ser_i : in std_ulogic;
done_o : out std_ulogic);
end component;
signal ser : std_ulogic;
begin
seqgen_i0 : seqgen
port map (
clk => CLOCK_50,
rst_n => KEY0,
ctrl_i => SW,
ser_o => ser);
EXP_PIN2 <= CLOCK_50;
EXP_PIN4 <= ser;
EXP_PIN6 <= '0';
LEDR(3 downto 0) <= SW;
LEDR(9 downto 4) <= "000000";
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity seqdet is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
ser_i : in std_ulogic;
done_o : out std_ulogic);
end entity;
architecture rtl of seqdet is
begin
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity seqgen is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
ctrl_i : in std_ulogic_vector(3 downto 0);
ser_o : out std_ulogic);
end entity;
architecture rtl of seqgen is
-- LFSR signals
signal en : std_ulogic;
signal sr, newsr: std_ulogic_vector(39 downto 1);
-- Counter signals
signal cnt,newcnt,startcnt : unsigned(38 downto 0);
signal ld : std_ulogic;
type state_t is (LOAD, RUN);
signal state : state_t;
begin
-- Linear Feedback Shift Register
sr <= (others => '1') when rst_n = '0' else newsr when en = '1' and rising_edge(clk);
newsr(1) <= sr(39) xor sr(35);
newsr(39 downto 2) <= sr(38 downto 1);
-- Downcounter
cnt <= (others => '0') when rst_n = '0' else newcnt when rising_edge(clk);
with ctrl_i select
startcnt <=
to_unsigned(143, cnt'length) when "0000",
to_unsigned(400000000, cnt'length) when "0001",
to_unsigned(1000000, cnt'length) when "0010",
to_unsigned(10000000, cnt'length) when "0011",
to_unsigned(100000000, cnt'length) when "0100",
to_unsigned(999, cnt'length) when others;
newcnt <= startcnt when ld = '1' else
(others => '0') when cnt = 0 else
cnt - 1;
en <= '1' when cnt > 0 else '0';
-- Statemachine to control the sequence generator
state <= LOAD when rst_n = '0' else RUN when rising_edge(clk);
ld <= '1' when state = LOAD else '0';
-- Output
ser_o <= sr(1);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity t_de1_seq is
end;
architecture tbench of t_de1_seq is
component de1_seq is
port ( CLOCK_50 : in std_ulogic;
SW : in std_ulogic_vector(3 downto 0);
KEY0 : in std_ulogic;
EXP_PIN2 : out std_ulogic;
EXP_PIN4 : out std_ulogic;
EXP_PIN6 : out std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end component;
signal redleds : std_ulogic_vector(9 downto 0);
signal clk, rst_n : std_ulogic;
signal simstop : boolean := false;
signal exp2, exp4, exp6 : std_ulogic;
signal schalter : std_ulogic_vector(3 downto 0) := "0000";
begin
de1_seq_i0 : de1_seq
port map (
CLOCK_50 => clk,
SW => schalter,
KEY0 => rst_n,
EXP_PIN2 => exp2,
EXP_PIN4 => exp4,
EXP_PIN6 => exp6,
LEDR => redleds);
rst_n <= '1', '0' after 20 ns, '1' after 40 ns;
clk_p : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if simstop then
wait;
end if;
end process clk_p;
-- This is the process where the switches are switched.
schalter_p : process
begin
wait for 100 us;
simstop <= true;
wait;
end process schalter_p;
end; -- architecture
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment