Commit e5823509 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

modified synthesis targets

parent 9d0098db
......@@ -16,13 +16,12 @@
@echo '"make" does intentionally nothing. Type:'
@echo ' "make qproject" to create a new quartus project'
@echo ' "make compile" to process through all design steps: map, fit, asm'
@echo ' "make compile" synthesize the design'
@echo ' "make prog" to configure programmable device'
@echo ' "make quartus" to start quartus graphical user interface'
@echo ' "make clean" to remove all generated files'
qproject: flowsummary.log
compile: flowsummary.log
flowsummary.log: $(SOURCE_FILES)
# assign VHDL design files
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