Commit e651ddb6 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

update cnt15 rtl code

The existing solution for the cnt15 was based on integer and
process. Changed to unsigned and concurrent signal assignments.
parent 0c45fdda
......@@ -38,6 +38,7 @@ set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
set_location_assignment PIN_L1 -to CLOCK_50
......
......@@ -17,31 +17,16 @@ end entity;
architecture rtl of cnt15 is
signal cnt, new_cnt : integer range 0 to 13;
signal cnt, new_cnt : unsigned(3 downto 0);
begin
process(clk, rst_n)
begin
if rst_n = '0' then
cnt <= 0;
elsif rising_edge(clk) then
cnt <= new_cnt;
end if;
end process;
process(ld_i, cnt)
begin
if ld_i = '1' then
new_cnt <= 13;
elsif cnt = 0 then
new_cnt <= 0;
else
new_cnt <= cnt - 1;
end if;
end process;
cnt <= "0000" when rst_n = '0' else new_cnt when rising_edge(clk);
new_cnt <= to_unsigned(13, 4) when ld_i = '1' else
cnt when cnt = 0 else cnt - 1;
done_o <= '1' when cnt = 0 else '0';
cnt_o <= std_ulogic_vector(to_unsigned(cnt,cnt_o'length));
cnt_o <= std_ulogic_vector(cnt);
end architecture rtl;
......@@ -3,6 +3,7 @@ use ieee.std_logic_1164.all;
entity de1_cnt15 is
port ( SW : in std_ulogic_vector(9 downto 0);
CLOCK_50 : in std_ulogic;
KEY : in std_ulogic_vector(3 downto 0);
HEX0 : out std_ulogic_vector(6 downto 0);
LEDG : out std_ulogic_vector(7 downto 0); -- green LEDs
......@@ -30,7 +31,7 @@ begin
cnt15_i0 : cnt15
port map (
clk => KEY(1),
clk => CLOCK_50,
rst_n => KEY(0),
ld_i => SW(0),
done_o => LEDG(2),
......
......@@ -8,6 +8,7 @@ architecture tbench of t_de1_cnt15 is
component de1_cnt15 is
port ( SW : in std_ulogic_vector(9 downto 0);
CLOCK_50 : in std_ulogic;
KEY : in std_ulogic_vector(3 downto 0);
HEX0 : out std_ulogic_vector(6 downto 0);
LEDG : out std_ulogic_vector(7 downto 0); -- green LEDs
......@@ -26,6 +27,7 @@ begin
port map (
SW(0) => d,
SW(9 downto 1) => "000000000",
CLOCK_50 => clk,
KEY(0) => rst_n,
KEY(1) => clk,
KEY(3 downto 2) => "00",
......@@ -52,7 +54,7 @@ begin
wait until rising_edge(rst_n);
wait until falling_edge(clk);
d <= '1';
wait for 100 ns;
wait for 300 ns;
d <= '0';
wait for 400 ns;
simstop <= true;
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment