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Commit e7835729 authored by Friedrich Beckmann's avatar Friedrich Beckmann
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removed vhd source files

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src/add1_truthtable.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : add1
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 1-bit adder
-- function modelled as a truth table
-- using a case statement in a process
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY add1 IS
PORT (a_i : IN std_ulogic; -- operand a
b_i : IN std_ulogic; -- operand b
ci_i : IN std_ulogic; -- carry in
sum_o : OUT std_ulogic; -- sum
co_o : OUT std_ulogic -- carry out
);
END add1;
ARCHITECTURE truthtable OF add1 IS
BEGIN
fulladder_p : PROCESS (ci_i, b_i, a_i)
VARIABLE inputs_v : std_ulogic_vector(2 DOWNTO 0); -- temp input variable
VARIABLE outputs_v : std_ulogic_vector(1 DOWNTO 0); -- temp output variable
BEGIN
inputs_v := (ci_i, b_i, a_i); -- concatenate single signals to a vector
CASE inputs_v IS
WHEN "000" => outputs_v := "00";
WHEN "001" => outputs_v := "10";
WHEN "010" => outputs_v := "10";
WHEN "011" => outputs_v := "01";
WHEN "100" => outputs_v := "10";
WHEN "101" => outputs_v := "01";
WHEN "110" => outputs_v := "01";
WHEN "111" => outputs_v := "11";
WHEN OTHERS => outputs_v := "XX";
END CASE;
sum_o <= outputs_v(1); -- split vector elements ...
co_o <= outputs_v(0); -- ... to individual signals
END PROCESS fulladder_p;
END truthtable;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/add4_rtl.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : add4
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 4-bit adder
-- function modelled by '+'-operator
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY add4 IS
PORT (a_i : IN std_ulogic_vector(3 DOWNTO 0); -- operand a
b_i : IN std_ulogic_vector(3 DOWNTO 0); -- operand b
ci_i : IN std_ulogic; -- carry in
sum_o : OUT std_ulogic_vector(3 DOWNTO 0); -- sum
co_o : OUT std_ulogic -- carry out
);
END add4;
ARCHITECTURE rtl OF add4 IS
SIGNAL temp_sum : unsigned(4 DOWNTO 0);
BEGIN
-- (co_o,sum_o) <= ('0' & unsigned(a_i)) + unsigned(b_i) + unsigned'(0 => ci_i);
temp_sum <= ('0' & unsigned(a_i)) + unsigned(b_i) + unsigned'(0 => ci_i);
sum_o <= std_ulogic_vector(temp_sum(3 DOWNTO 0));
co_o <= temp_sum(4);
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/add4_structure.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : add4
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 4-bit adder
-- function modelled by cascading 1-bit adder modules
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY add4 IS
PORT (a_i : IN std_ulogic_vector(3 DOWNTO 0); -- operand a
b_i : IN std_ulogic_vector(3 DOWNTO 0); -- operand b
ci_i : IN std_ulogic; -- carry in
sum_o : OUT std_ulogic_vector(3 DOWNTO 0); -- sum
co_o : OUT std_ulogic -- carry out
);
END add4;
ARCHITECTURE structure OF add4 IS
COMPONENT add1
PORT(a_i : IN std_ulogic;
b_i : IN std_ulogic;
ci_i : IN std_ulogic;
sum_o : OUT std_ulogic;
co_o : OUT std_ulogic
);
END COMPONENT;
SIGNAL carry0 : std_ulogic;
SIGNAL carry1 : std_ulogic;
SIGNAL carry2 : std_ulogic;
BEGIN
inst0 : add1
PORT MAP(a_i => a_i(0),
b_i => b_i(0),
ci_i => ci_i,
sum_o => sum_o(0),
co_o => carry0);
inst1 : add1
PORT MAP(a_i => a_i(1),
b_i => b_i(1),
ci_i => carry0,
sum_o => sum_o(1),
co_o => carry1);
inst2 : add1
PORT MAP(a_i => a_i(2),
b_i => b_i(2),
ci_i => carry1,
sum_o => sum_o(2),
co_o => carry2);
inst3 : add1
PORT MAP(a_i => a_i(3),
b_i => b_i(3),
ci_i => carry2,
sum_o => sum_o(3),
co_o => co_o);
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/and2gate_equation.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : and2gate
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 2-input AND Gate
-- function modelled by logic equation
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY and2gate IS
PORT (a_i : IN std_ulogic; -- data input a
b_i : IN std_ulogic; -- data input b
y_o : OUT std_ulogic -- data output y
);
END and2gate;
ARCHITECTURE equation OF and2gate IS
BEGIN
y_o <= a_i AND b_i;
END equation;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/binto7segment_stimuli.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : binto7segment_stimuli
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: stimuli for verification of binary-to-7-segment decoder
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY binto7segment_stimuli IS
PORT (
stimuli_o : OUT std_ulogic_vector(3 DOWNTO 0)
);
END binto7segment_stimuli;
ARCHITECTURE stimuli OF binto7segment_stimuli IS
-- definition of a clock period
CONSTANT period : time := 10 ns;
BEGIN
stimuli_p : PROCESS
BEGIN
stimuli_o <= "0000";
WAIT FOR period;
stimuli_o <= "0001";
WAIT FOR period;
stimuli_o <= "0010";
WAIT FOR period;
stimuli_o <= "0011";
WAIT FOR period;
stimuli_o <= "0100";
WAIT FOR period;
stimuli_o <= "0101";
WAIT FOR period;
stimuli_o <= "0110";
WAIT FOR period;
stimuli_o <= "0111";
WAIT FOR period;
stimuli_o <= "1000";
WAIT FOR period;
stimuli_o <= "1001";
WAIT FOR period;
stimuli_o <= "1010";
WAIT FOR period;
stimuli_o <= "1011";
WAIT FOR period;
stimuli_o <= "1100";
WAIT FOR period;
stimuli_o <= "1101";
WAIT FOR period;
stimuli_o <= "1110";
WAIT FOR period;
stimuli_o <= "1111";
WAIT FOR period;
WAIT;
END PROCESS;
END stimuli;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/binto7segment_truthtable.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : binto7segment
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: binary-to-7-segment decoder
-- function modelled as a truth table
-- using a case statement in a process
-- segments get illuminated by a low-active signal
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY binto7segment IS
PORT (bin_i : IN std_ulogic_vector(3 DOWNTO 0);
segments_o : OUT std_ulogic_vector(6 DOWNTO 0)
);
END binto7segment;
ARCHITECTURE truthtable OF binto7segment IS
-- seven-segment positions
--
-- segment positions input vector index segment name
-- a 0 => a
-- --- 1 => b
-- f | | b 2 => c
-- --- <- g 3 => d
-- e | | c 4 => e
-- --- 5 => f
-- d 6 => g
BEGIN
decoder_p : PROCESS (bin_i)
BEGIN -- index number displayed
CASE bin_i IS -- 6543210
WHEN "0000" => segments_o <= "1000000"; -- 0
WHEN "0001" => segments_o <= "1111001"; -- 1
WHEN "0010" => segments_o <= "0100100"; -- 2
WHEN "0011" => segments_o <= "0110000"; -- 3
WHEN "0100" => segments_o <= "0011001"; -- 4
WHEN "0101" => segments_o <= "0010010"; -- 5
WHEN "0110" => segments_o <= "0000010"; -- 6
WHEN "0111" => segments_o <= "1111000"; -- 7
WHEN "1000" => segments_o <= "0000000"; -- 8
WHEN "1001" => segments_o <= "0010000"; -- 9
WHEN "1010" => segments_o <= "0001000"; -- A
WHEN "1011" => segments_o <= "0000011"; -- b
WHEN "1100" => segments_o <= "1000110"; -- C
WHEN "1101" => segments_o <= "0100001"; -- d
WHEN "1110" => segments_o <= "0000110"; -- E
WHEN "1111" => segments_o <= "0001110"; -- F
WHEN OTHERS => segments_o <= "XXXXXXX";
END CASE;
END PROCESS decoder_p;
END truthtable;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/cnt4up_structure.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : cnt4up
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 4-Bit Up-Counter
-- including a low-active asynchronous reset input rst_ni
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cnt4up IS
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
count_o : OUT std_ulogic_vector(3 DOWNTO 0)
);
END cnt4up;
ARCHITECTURE structure OF cnt4up IS
COMPONENT dreg
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
d_i : IN std_ulogic_vector(3 DOWNTO 0);
q_o : OUT std_ulogic_vector(3 DOWNTO 0));
END COMPONENT;
COMPONENT add4
PORT (
a_i : IN std_ulogic_vector(3 DOWNTO 0);
b_i : IN std_ulogic_vector(3 DOWNTO 0);
ci_i : IN std_ulogic;
sum_o : OUT std_ulogic_vector(3 DOWNTO 0);
co_o : OUT std_ulogic);
END COMPONENT;
SIGNAL next_state, current_state : std_ulogic_vector(3 DOWNTO 0);
BEGIN
incrementer : ENTITY work.add4(structure)
PORT MAP (
a_i => B"0001",
b_i => current_state,
ci_i => '0',
sum_o => next_state,
co_o => OPEN);
state_register : ENTITY work.dreg(structure)
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
d_i => next_state,
q_o => current_state);
counter_output : count_o <= current_state;
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/cntdn_structure.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : cntdn
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: n-Bit Down-Counter
-- including a low-active asynchronous reset input rst_ni
-- and a high-active enable input en_pi
-- additionally, a high_active output signal tc_o is produced,
-- when the counter reaches it's minimum value
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY cntdn IS
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector(3 DOWNTO 0);
tc_o : OUT std_ulogic
);
END cntdn;
ARCHITECTURE structure OF cntdn IS
COMPONENT dregen
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
d_i : IN std_ulogic_vector(3 DOWNTO 0);
q_o : OUT std_ulogic_vector(3 DOWNTO 0));
END COMPONENT;
COMPONENT add4
PORT (
a_i : IN std_ulogic_vector(3 DOWNTO 0);
b_i : IN std_ulogic_vector(3 DOWNTO 0);
ci_i : IN std_ulogic;
sum_o : OUT std_ulogic_vector(3 DOWNTO 0);
co_o : OUT std_ulogic);
END COMPONENT;
SIGNAL next_state, current_state : std_ulogic_vector(3 DOWNTO 0);
BEGIN
decrementer : ENTITY work.add4(structure)
PORT MAP (
a_i => B"1111",
b_i => current_state,
ci_i => '0',
sum_o => next_state,
co_o => OPEN);
state_register : ENTITY work.dregen(rtl)
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
en_pi => en_pi,
d_i => next_state,
q_o => current_state);
counter_output : count_o <= current_state;
terminal_count : tc_o <= NOT (current_state(3) OR current_state(2) OR
current_state(1) OR current_state(0));
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/cntdnmodm_rtl.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : cntdnmodm
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Modulo-m n-Bit Down-Counter
-- including a low-active asynchronous reset input rst_ni
-- and a high-active enable input en_pi
-- additionally, a high_active output signal tc_o is produced,
-- when the counter reaches it's minimum value
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY cntdnmodm IS
GENERIC (
n : natural := 4; -- counter width
m : natural := 9); -- modulo value
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector(n-1 DOWNTO 0);
tc_o : OUT std_ulogic
);
END cntdnmodm;
ARCHITECTURE rtl OF cntdnmodm IS
-- CONSTANT n : natural := count_o'length; -- counter width
SIGNAL next_state, current_state : unsigned(n - 1 DOWNTO 0);
BEGIN
decrementer : next_state <= to_unsigned(m-1, n) WHEN current_state = 0 ELSE
current_state - 1;
state_register : PROCESS (rst_ni, clk_i)
CONSTANT zero : unsigned(current_state'length-1 DOWNTO 0) :=(OTHERS => '0');
BEGIN
IF rst_ni = '0' THEN
current_state <= zero;
ELSIF rising_edge(clk_i) THEN
IF en_pi = '1' THEN
current_state <= next_state;
END IF;
END IF;
END PROCESS state_register;
counter_output : count_o <= std_ulogic_vector(current_state);
terminal_count : tc_o <= '1' WHEN current_state = 0 ELSE '0';
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/cntupen_structure.vhd deleted 100644 → 0
View file @ 6c8ec948
-------------------------------------------------------------------------------
-- Module : cntupen
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: Up-Counter
-- including a low-active asynchronous reset input rst_ni
-- and a high-active enable input en_pi
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cntupen IS
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector(3 DOWNTO 0)
);
END cntupen;
ARCHITECTURE structure OF cntupen IS
COMPONENT dregen
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
d_i : IN std_ulogic_vector(3 DOWNTO 0);
q_o : OUT std_ulogic_vector(3 DOWNTO 0));
END COMPONENT;
COMPONENT add4
PORT (
a_i : IN std_ulogic_vector(3 DOWNTO 0);
b_i : IN std_ulogic_vector(3 DOWNTO 0);
ci_i : IN std_ulogic;
sum_o : OUT std_ulogic_vector(3 DOWNTO 0);
co_o : OUT std_ulogic);
END COMPONENT;