Commit e86cf414 authored by Johann Faerber's avatar Johann Faerber
Browse files

added design add1

parent 3812ea0b
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
# ----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : de1_add1
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: test the module add1 on a DE1 prototype board
-- connecting device under test (DUT) add1
-- to input/output signals of the DE1 prototype board
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY de1_add1 IS
PORT (
SW : IN std_ulogic_vector(2 DOWNTO 0); -- Toggle Switch[2:0]
LEDR : OUT std_ulogic_vector(1 DOWNTO 0) -- LED Red[1:0]
);
END de1_add1;
ARCHITECTURE structure OF de1_add1 IS
COMPONENT add1
PORT (
a_i : IN std_ulogic;
b_i : IN std_ulogic;
ci_i : IN std_ulogic;
sum_o : OUT std_ulogic;
co_o : OUT std_ulogic);
END COMPONENT;
BEGIN
-- connecting device under test with peripheral elements
DUT : add1
PORT MAP (
a_i => SW(0),
b_i => SW(1),
ci_i => SW(2),
sum_o => LEDR(0),
co_o => LEDR(1)
);
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: - mandatory design directory structure (see end of file)
# - scripts/quartus_project_settings.tcl
# - scripts/de1_$(PROJECT)_pins.tcl
#
# - modify and copy it to pnr/de1_(PROJECT)/makefile
# - specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
###################################################################
SIM_PROJECT_NAME = add1
PROJECT = de1_$(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./$(PROJECT)_structure.vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# Prerequisite: mandatory design directory structure (see end of file)
#
# - modify and copy it to sim/(PROJECT)/makefile
# - Specify the name of the design (PROJECT)
# - and the list of source files used (SOURCE_FILES)
###################################################################
PROJECT = add1
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
./t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: see end of file
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/add1_truthtable.vhd \
-------------------------------------------------------------------------------
-- Module : t_add1
-------------------------------------------------------------------------------
-- Author : <haf@fh-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2011 <haf@fh-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "add1"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_add1 IS
END t_add1;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_add1 IS
COMPONENT add1
PORT (
a_i : IN std_ulogic;
b_i : IN std_ulogic;
ci_i : IN std_ulogic;
sum_o : OUT std_ulogic;
co_o : OUT std_ulogic);
END COMPONENT;
-- definition of a clock period
CONSTANT period : time := 10 ns;
-- component ports
SIGNAL a_i : std_ulogic;
SIGNAL b_i : std_ulogic;
SIGNAL ci_i : std_ulogic;
SIGNAL sum_o : std_ulogic;
SIGNAL co_o : std_ulogic;
BEGIN -- tbench
-- component instantiation
MUV : add1
PORT MAP (
a_i => a_i,
b_i => b_i,
ci_i => ci_i,
sum_o => sum_o,
co_o => co_o);
stimuli_p : PROCESS
-- purpose: apply stimuli to input signals of module under test
PROCEDURE apply_stimuli (
CONSTANT ci_stim, b_stim, a_stim : IN std_ulogic) IS
BEGIN -- apply_stimuli
a_i <= a_stim;
b_i <= b_stim;
ci_i <= ci_stim;
WAIT FOR period;
END PROCEDURE apply_stimuli;
BEGIN
a_i <= '0'; -- set a value to input a_i
b_i <= '0'; -- set a value to input b_i
ci_i <= '0'; -- set a value to input ci_i
WAIT FOR period; -- values are assigned here
a_i <= '1'; -- change value of a_i
WAIT FOR period;
a_i <= '0'; -- change value of a_i
b_i <= '1'; -- change value of b_i
WAIT FOR period;
-- alternatively, a local procedure can be used to assign input values:
-- apply_stimuli('0', '0', '0');
-- apply_stimuli('0', '0', '1');
-- apply_stimuli('0', '1', '0');
apply_stimuli('0', '1', '1');
apply_stimuli('1', '0', '0');
apply_stimuli('1', '0', '1');
apply_stimuli('1', '1', '0');
apply_stimuli('1', '1', '1');
WAIT;
END PROCESS;
END tbench;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : add1
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 1-bit adder
-- function modelled as a truth table
-- using a case statement in a process
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY add1 IS
PORT (a_i : IN std_ulogic; -- operand a
b_i : IN std_ulogic; -- operand b
ci_i : IN std_ulogic; -- carry in
sum_o : OUT std_ulogic; -- sum
co_o : OUT std_ulogic -- carry out
);
END add1;
ARCHITECTURE truthtable OF add1 IS
BEGIN
fulladder_p : PROCESS (ci_i, b_i, a_i)
VARIABLE inputs_v : std_ulogic_vector(2 DOWNTO 0); -- temp input variable
VARIABLE outputs_v : std_ulogic_vector(1 DOWNTO 0); -- temp output variable
BEGIN
inputs_v := (ci_i, b_i, a_i); -- concatenate single signals to a vector
CASE inputs_v IS
WHEN "000" => outputs_v := "00";
WHEN "001" => outputs_v := "10";
WHEN "010" => outputs_v := "10";
WHEN "011" => outputs_v := "01";
WHEN "100" => outputs_v := "10";
WHEN "101" => outputs_v := "01";
WHEN "110" => outputs_v := "01";
WHEN "111" => outputs_v := "11";
WHEN OTHERS => outputs_v := "XX";
END CASE;
sum_o <= outputs_v(1); -- split vector elements ...
co_o <= outputs_v(0); -- ... to individual signals
END PROCESS fulladder_p;
END truthtable;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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