in all design projects of lab #3

hence, adding add1(truthtable) to the makefile.sources

pnr/de1_mux2to1/de1_mux2to1_pins.qsf
pnr/de1_binto7segment/de1_binto7segment_pin.qsf

as a format for importing pin assignments manually

pnr/de1_mux2to1/de1_mux2to1.qpf
pnr/de1_mux2to1/de1_mux2to1.qsf

and design files
pnr/de1_binto7segment/de1_binto7segment.qpf
pnr/de1_binto7segment/de1_binto7segment.qsf

added doc/ReadMe.md

which follows git markdown syntax

Merge branch 'master' of https://git.etech.fh-augsburg.de/friedrich.beckmann/digitaltechnikpraktikum

create_quartus_project_settings.tcl

necessary changes in pnr/makefile and sim/makefile

scripts/modelsim.ini

the following line at the end

# do not delete this line
# -----------------------------------------------------------------------------

to start vsim as background process, added & for target sim

- added file scripts/design_project_directory_structure.txt
- added credentials for Friedrich Beckmann in header blocks
- added appropriate comments to understand makefiles
- moved testbenches and test environment source files to src dir

added -modelsimini ../../scripts/modelsim.ini