Hans hatte doch keine Lust. Habe ich im Readme ergänzt.

Ich habe das Repository von eds1 kopiert und im Readme den
Hinweis auf das Sommersemester 2022 eingefügt.

This is the uart transmitter developed during SS19. It is only
the transmitter datapath and the testbench. The state controller
is missing. The datapath is based on the shift register idea
including the stopbit.

I added the searchJK and the rx_byte_compare procedure to a package p_4b5b
to have the test function available in the t_4b5b and t_framesync testbench.
I added the stringtx module and the framesync module.

The tx4b5b module can transmit a stream of bytes. The bytes
are framed with the 4b5b framing method.

counter1st was implemented based on process and integer type.
I added unsigned and concurrent signal assignment variants

counter1st with process style counter description including
self checking testbench