fixed sensitivity list of uart_tx

src/stringtx_rtl.vhd

@@ -35,7 +35,7 @@ begin
   
   cstate <= IDLE_S when rst_n = '0' else nstate when rising_edge(clk);
   
-  ns_p : process (cstate, done_i, strstart_i)
+  ns_p : process (cstate, done_i, strstart_i, idx)
   begin
     idx_inc <= '0';
     start_o <= '0';