add sdc file generation to pnr/makefile

pnr/makefile

-## ----------------------------------------------------------------------------
-## Script     : makefile
-## ----------------------------------------------------------------------------
-## Author     : Johann Faerber, Friedrich Beckmann
-## Company    : University of Applied Sciences Augsburg
-## ----------------------------------------------------------------------------
-## Description: This makefile allows automating design flow with Quartus,
-##              it is based on a design directory structure shown at 
-##              the end of this file.
-## ----------------------------------------------------------------------------
-
-###################################################################
-# Main Targets
-#
-###################################################################
 
 help:
 	@echo '"make" does intentionally nothing. Type:'
@@ -22,10 +7,15 @@ help:
 	@echo '  "make quartus" to start quartus graphical user interface'
 	@echo '  "make clean" to remove all generated files'
 
+$(PROJECT).sdc:
+	# create a default timing constraint file assuming CLOCK_50
+	echo "create_clock -period 20.000 -name CLOCK_50 CLOCK_50" > $(PROJECT).sdc
+	echo "set_input_delay -clock CLOCK_50 2 [all_inputs]" >> $(PROJECT).sdc
+	echo "set_output_delay -clock CLOCK_50 2 [all_outputs]" >> $(PROJECT).sdc
 
 qproject: $(PROJECT).qpf
 
-$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl ../../sim/$(SIM_PROJECT_NAME)/makefile.sources $(PROJECT).sdc
 	# assign VHDL design files
 	rm -rf quartus_vhdl_source_files.tcl
 	for source_file in $(SOURCE_FILES); do \