changed signal name to z

mclk.vhd

@@ -7,7 +7,7 @@ end;
 architecture rtl of mclk is
   signal d : std_ulogic;
   signal k : integer range 0 to 15;
-  signal q : std_ulogic_vector(3 downto 0);
+  signal z : std_ulogic_vector(3 downto 0);
 begin
 
 end architecture;