Commit 3a32879e authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

added matlab fpga-in-the-loop Altera DE1 SoC configuration file

this is the board configuration file to run fpga in the loop simulations
parent 80992d1c
<?xml version="1.0" encoding="utf-8"?>
<FPGABoard Version="1.0">
<BoardName>Altera DE1-SoC</BoardName>
<FPGA Device="5CSEMA5F31C6" Family="Cyclone V" JTAGChainPosition="2" Package="" Speed="" Vendor="Altera">
<Interface>
<Type>Altera JTAG</Type>
</Interface>
<Interface>
<Type>Clock</Type>
<Parameter ID="ClockType">Single-Ended</Parameter>
<Parameter ID="Frequency">50</Parameter>
<Signal>
<SignalName>Clock</SignalName>
<Description>Clock</Description>
<Direction>in</Direction>
<BitWidth>1</BitWidth>
<FPGAPin>AF14</FPGAPin>
<IOStandard>3.3-V LVCMOS</IOStandard>
</Signal>
</Interface>
<Interface>
<Type>Reset</Type>
<Parameter ID="ActiveLevel">Active-Low</Parameter>
<Signal>
<SignalName>Reset</SignalName>
<Description>Reset</Description>
<Direction>in</Direction>
<BitWidth>1</BitWidth>
<FPGAPin>AA14</FPGAPin>
<IOStandard>3.3-V LVCMOS</IOStandard>
</Signal>
</Interface>
<Interface>
<Type>User-defined I/O interface</Type>
<Signal>
<SignalName>LED</SignalName>
<Description>Red LEDs</Description>
<Direction>out</Direction>
<BitWidth>10</BitWidth>
<FPGAPin>V16, W16, V17, V18, W17, W19, Y19, W20, W21, Y21</FPGAPin>
<IOStandard/>
</Signal>
<Signal>
<SignalName>SW</SignalName>
<Description>Switches</Description>
<Direction>in</Direction>
<BitWidth>10</BitWidth>
<FPGAPin>AB12, AC12, AF9, AF10, AD11, AD12, AE11, AC9, AD10, AE12</FPGAPin>
<IOStandard/>
</Signal>
</Interface>
</FPGA>
</FPGABoard>
\ No newline at end of file
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