Commit 650c9669 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

added de1_simpletrans

This is the simple system clock equal to data clock data
transmission with 6 Bit LFSR as Scrambler and Descrambler.
parent 371647d4
# Pin Configuration
set_location_assignment PIN_AB12 -to SW[0]
set_location_assignment PIN_AC12 -to SW[1]
set_location_assignment PIN_AF9 -to SW[2]
set_location_assignment PIN_AF10 -to SW[3]
set_location_assignment PIN_AD11 -to SW[4]
set_location_assignment PIN_AD12 -to SW[5]
set_location_assignment PIN_AE11 -to SW[6]
set_location_assignment PIN_AC9 -to SW[7]
set_location_assignment PIN_AD10 -to SW[8]
set_location_assignment PIN_AE12 -to SW[9]
set_location_assignment PIN_V16 -to LEDR[0]
set_location_assignment PIN_W16 -to LEDR[1]
set_location_assignment PIN_V17 -to LEDR[2]
set_location_assignment PIN_V18 -to LEDR[3]
set_location_assignment PIN_W17 -to LEDR[4]
set_location_assignment PIN_W19 -to LEDR[5]
set_location_assignment PIN_Y19 -to LEDR[6]
set_location_assignment PIN_W20 -to LEDR[7]
set_location_assignment PIN_W21 -to LEDR[8]
set_location_assignment PIN_Y21 -to LEDR[9]
set_location_assignment PIN_AA14 -to KEY0
set_location_assignment PIN_AF14 -to CLOCK_50
set_location_assignment PIN_AK27 -to DAC_CLK_A
set_location_assignment PIN_AK26 -to DAC_CLK_B
set_location_assignment PIN_AK28 -to DAC_DA[0]
set_location_assignment PIN_AE24 -to DAC_DA[10]
set_location_assignment PIN_AD24 -to DAC_DA[11]
set_location_assignment PIN_AC23 -to DAC_DA[12]
set_location_assignment PIN_AA21 -to DAC_DA[13]
set_location_assignment PIN_AJ27 -to DAC_DA[1]
set_location_assignment PIN_AK29 -to DAC_DA[2]
set_location_assignment PIN_AH27 -to DAC_DA[3]
set_location_assignment PIN_AH24 -to DAC_DA[4]
set_location_assignment PIN_AG25 -to DAC_DA[5]
set_location_assignment PIN_AG26 -to DAC_DA[6]
set_location_assignment PIN_AF26 -to DAC_DA[7]
set_location_assignment PIN_AF25 -to DAC_DA[8]
set_location_assignment PIN_AE23 -to DAC_DA[9]
set_location_assignment PIN_AE22 -to DAC_DB[0]
set_location_assignment PIN_AK23 -to DAC_DB[10]
set_location_assignment PIN_AK24 -to DAC_DB[11]
set_location_assignment PIN_AJ24 -to DAC_DB[12]
set_location_assignment PIN_AH25 -to DAC_DB[13]
set_location_assignment PIN_AF24 -to DAC_DB[1]
set_location_assignment PIN_AD21 -to DAC_DB[2]
set_location_assignment PIN_AF23 -to DAC_DB[3]
set_location_assignment PIN_AH22 -to DAC_DB[4]
set_location_assignment PIN_AK22 -to DAC_DB[5]
set_location_assignment PIN_AG22 -to DAC_DB[6]
set_location_assignment PIN_AJ22 -to DAC_DB[7]
set_location_assignment PIN_AH23 -to DAC_DB[8]
set_location_assignment PIN_AG23 -to DAC_DB[9]
set_location_assignment PIN_AC22 -to DAC_MODE
set_location_assignment PIN_AJ26 -to DAC_WRT_A
set_location_assignment PIN_AA20 -to DAC_WRT_B
set_location_assignment PIN_AA18 -to ADC_CLK_A
set_location_assignment PIN_AE17 -to ADC_CLK_B
set_location_assignment PIN_AJ21 -to ADC_OEB_A
set_location_assignment PIN_AG20 -to ADC_OEB_B
set_location_assignment PIN_AF18 -to POWER_ON
set_location_assignment PIN_AA19 -to ADC_DA[0]
set_location_assignment PIN_AF20 -to ADC_DA[10]
set_location_assignment PIN_AF19 -to ADC_DA[11]
set_location_assignment PIN_AF21 -to ADC_DA[12]
set_location_assignment PIN_AG21 -to ADC_DA[13]
set_location_assignment PIN_AC20 -to ADC_DA[1]
set_location_assignment PIN_AH19 -to ADC_DA[2]
set_location_assignment PIN_AH20 -to ADC_DA[3]
set_location_assignment PIN_AJ20 -to ADC_DA[4]
set_location_assignment PIN_AK21 -to ADC_DA[5]
set_location_assignment PIN_AD19 -to ADC_DA[6]
set_location_assignment PIN_AE18 -to ADC_DA[7]
set_location_assignment PIN_AD20 -to ADC_DA[8]
set_location_assignment PIN_AE19 -to ADC_DA[9]
set_location_assignment PIN_Y17 -to ADC_DB[0]
set_location_assignment PIN_AG16 -to ADC_DB[10]
set_location_assignment PIN_AF16 -to ADC_DB[11]
set_location_assignment PIN_AE16 -to ADC_DB[12]
set_location_assignment PIN_AG17 -to ADC_DB[13]
set_location_assignment PIN_Y18 -to ADC_DB[1]
set_location_assignment PIN_AK16 -to ADC_DB[2]
set_location_assignment PIN_AK19 -to ADC_DB[3]
set_location_assignment PIN_AK18 -to ADC_DB[4]
set_location_assignment PIN_AJ19 -to ADC_DB[5]
set_location_assignment PIN_AJ17 -to ADC_DB[6]
set_location_assignment PIN_AH18 -to ADC_DB[7]
set_location_assignment PIN_AJ16 -to ADC_DB[8]
set_location_assignment PIN_AH17 -to ADC_DB[9]
set_location_assignment PIN_AC18 -to ADC_OTR_A
set_location_assignment PIN_AD17 -to ADC_OTR_B
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
SIM_PROJECT_NAME = de1_simpletrans
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
PROJECT = de1_simpletrans
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/de1_simpletrans_rtl.vhd \
../../src/dacint_rtl.vhd \
../../matlab/simpletrans/hdl_prj/hdlsrc/simpletrans/datagen.vhd \
../../matlab/simpletrans/hdl_prj/hdlsrc/simpletrans/datarec.vhd \
../../matlab/simpletrans/hdl_prj/hdlsrc/simpletrans/siggen.vhd
# do not delete this line
# -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity de1_simpletrans is
port ( CLOCK_50 : in std_ulogic;
SW : in std_ulogic_vector(9 downto 0);
KEY0 : in std_ulogic;
DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved
DAC_WRT_A : out std_ulogic;
DAC_WRT_B : out std_ulogic;
DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual
DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual
DAC_DA : out std_ulogic_vector(13 downto 0);
DAC_DB : out std_ulogic_vector(13 downto 0);
ADC_CLK_A : out std_ulogic;
ADC_CLK_B : out std_ulogic;
POWER_ON : out std_ulogic;
ADC_OEB_A : out std_ulogic;
ADC_OEB_B : out std_ulogic;
ADC_DA : in std_ulogic_vector(13 downto 0);
ADC_DB : in std_ulogic_vector(13 downto 0);
ADC_OTR_A : in std_ulogic;
ADC_OTR_B : in std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end entity;
architecture rtl of de1_simpletrans is
signal clk,rst_n : std_ulogic;
constant clk_enable : std_logic := '1';
signal dac_a, dac_b : std_logic_vector(13 downto 0);
signal adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0);
signal biterror_cnt : std_logic_vector(7 downto 0);
component dacint is
port( clk : in std_ulogic;
rst_n : in std_ulogic;
dac_a_i : in std_ulogic_vector(13 downto 0);
dac_a_o : out std_ulogic_vector(13 downto 0);
dac_b_i : in std_ulogic_vector(13 downto 0);
dac_b_o : out std_ulogic_vector(13 downto 0));
end component;
component siggen is
port( clk : IN std_logic;
rst_n : IN std_logic;
clk_enable : IN std_logic;
rx_data_i : IN std_logic_vector(13 DOWNTO 0); -- ufix14_En14
ce_out : OUT std_logic;
tx_data_o : OUT std_logic_vector(13 DOWNTO 0); -- ufix14_En14
biterror_cnt_o : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
end component;
begin
clk <= CLOCK_50;
rst_n <= KEY0;
LEDR(7 downto 0) <= std_ulogic_vector(biterror_cnt);
LEDR(8) <= ADC_OTR_B;
LEDR(9) <= ADC_OTR_A;
DAC_MODE <= '1'; --dual port
DAC_CLK_A <= clk;
DAC_CLK_B <= clk;
DAC_WRT_A <= clk;
DAC_WRT_B <= clk;
POWER_ON <= '1'; -- Switch ON DAC/ADC
dacint_i0 : dacint
port map (
clk => clk,
rst_n => rst_n,
dac_a_i => std_ulogic_vector(dac_a),
dac_a_o => DAC_DA,
dac_b_i => std_ulogic_vector(dac_b),
dac_b_o => DAC_DB);
siggen_i0 : siggen
port map (
clk => clk,
rst_n => rst_n,
clk_enable => clk_enable,
rx_data_i => std_logic_vector(adc_a_dat),
tx_data_o => dac_a,
biterror_cnt_o => biterror_cnt);
dac_b <= std_logic_vector(adc_a_dat); -- ADC A -> DAC B
-- ADC Section
ADC_CLK_A <= clk;
ADC_CLK_B <= clk;
ADC_OEB_A <= '0';
ADC_OEB_B <= '0';
adc_a_dat <= (others => '0') when rst_n = '0' else ADC_DA when rising_edge(clk);
adc_b_dat <= (others => '0') when rst_n = '0' else ADC_DB when rising_edge(clk);
end architecture rtl;
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