Commit 96157731 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

initial dac test

parent 1d1cec71
# Pin Configuration
set_location_assignment PIN_AB12 -to SW[0]
set_location_assignment PIN_AC12 -to SW[1]
set_location_assignment PIN_AF9 -to SW[2]
set_location_assignment PIN_AF10 -to SW[3]
set_location_assignment PIN_AD11 -to SW[4]
set_location_assignment PIN_AD12 -to SW[5]
set_location_assignment PIN_AE11 -to SW[6]
set_location_assignment PIN_AC9 -to SW[7]
set_location_assignment PIN_AD10 -to SW[8]
set_location_assignment PIN_AE12 -to SW[9]
set_location_assignment PIN_V16 -to LEDR[0]
set_location_assignment PIN_W16 -to LEDR[1]
set_location_assignment PIN_V17 -to LEDR[2]
set_location_assignment PIN_V18 -to LEDR[3]
set_location_assignment PIN_W17 -to LEDR[4]
set_location_assignment PIN_W19 -to LEDR[5]
set_location_assignment PIN_Y19 -to LEDR[6]
set_location_assignment PIN_W20 -to LEDR[7]
set_location_assignment PIN_W21 -to LEDR[8]
set_location_assignment PIN_Y21 -to LEDR[9]
set_location_assignment PIN_AA14 -to KEY0
set_location_assignment PIN_AF14 -to CLOCK_50
set_location_assignment PIN_AK27 -to DAC_CLK_A
set_location_assignment PIN_AK26 -to DAC_CLK_B
set_location_assignment PIN_AK28 -to DAC_DA[0]
set_location_assignment PIN_AE24 -to DAC_DA[10]
set_location_assignment PIN_AD24 -to DAC_DA[11]
set_location_assignment PIN_AC23 -to DAC_DA[12]
set_location_assignment PIN_AA21 -to DAC_DA[13]
set_location_assignment PIN_AJ27 -to DAC_DA[1]
set_location_assignment PIN_AK29 -to DAC_DA[2]
set_location_assignment PIN_AH27 -to DAC_DA[3]
set_location_assignment PIN_AH24 -to DAC_DA[4]
set_location_assignment PIN_AG25 -to DAC_DA[5]
set_location_assignment PIN_AG26 -to DAC_DA[6]
set_location_assignment PIN_AF26 -to DAC_DA[7]
set_location_assignment PIN_AF25 -to DAC_DA[8]
set_location_assignment PIN_AE23 -to DAC_DA[9]
set_location_assignment PIN_AE22 -to DAC_DB[0]
set_location_assignment PIN_AK23 -to DAC_DB[10]
set_location_assignment PIN_AK24 -to DAC_DB[11]
set_location_assignment PIN_AJ24 -to DAC_DB[12]
set_location_assignment PIN_AH25 -to DAC_DB[13]
set_location_assignment PIN_AF24 -to DAC_DB[1]
set_location_assignment PIN_AD21 -to DAC_DB[2]
set_location_assignment PIN_AF23 -to DAC_DB[3]
set_location_assignment PIN_AH22 -to DAC_DB[4]
set_location_assignment PIN_AK22 -to DAC_DB[5]
set_location_assignment PIN_AG22 -to DAC_DB[6]
set_location_assignment PIN_AJ22 -to DAC_DB[7]
set_location_assignment PIN_AH23 -to DAC_DB[8]
set_location_assignment PIN_AG23 -to DAC_DB[9]
set_location_assignment PIN_AC22 -to DAC_MODE
set_location_assignment PIN_AJ26 -to DAC_WRT_A
set_location_assignment PIN_AA20 -to DAC_WRT_B
set_location_assignment PIN_AA18 -to ADC_CLK_A
set_location_assignment PIN_AE17 -to ADC_CLK_B
set_location_assignment PIN_AJ21 -to ADC_OEB_A
set_location_assignment PIN_AG20 -to ADC_OEB_B
set_location_assignment PIN_AF18 -to POWER_ON
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
SIM_PROJECT_NAME = de1_dac
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
PROJECT = de1_dac
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/de1_dac_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity de1_dac is
port ( CLOCK_50 : in std_ulogic;
SW : in std_ulogic_vector(9 downto 0);
KEY0 : in std_ulogic;
DAC_MODE : out std_ulogic; --1=dual port, 0=interleaved
DAC_WRT_A : out std_ulogic;
DAC_WRT_B : out std_ulogic;
DAC_CLK_A : out std_ulogic; -- PLL_OUT_DAC0 in User Manual
DAC_CLK_B : out std_ulogic; -- PLL_OUT_DAC1 in User Manual
DAC_DA : out std_ulogic_vector(13 downto 0);
DAC_DB : out std_ulogic_vector(13 downto 0);
ADC_CLK_A : out std_ulogic;
ADC_CLK_B : out std_ulogic;
POWER_ON : out std_ulogic;
ADC_OEB_A : out std_ulogic;
ADC_OEB_B : out std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end entity;
architecture rtl of de1_dac is
signal clk,rst_n : std_ulogic;
signal cnt : unsigned(13 downto 0);
signal lfsr : std_ulogic_vector(13 downto 0);
signal phase_inc : unsigned(9 downto 0);
begin
clk <= CLOCK_50;
rst_n <= KEY0;
LEDR <= SW;
DAC_MODE <= '1'; --dual port
DAC_CLK_A <= clk;
DAC_CLK_B <= clk;
DAC_WRT_A <= clk;
DAC_WRT_B <= clk;
phase_inc <= unsigned(SW);
cnt <= (others => '0') when rst_n = '0' else cnt+phase_inc when falling_edge(clk);
DAC_DA <= (others => '1') when cnt = 0 else (others => '0');
--DAC_DA <= std_ulogic_vector(cnt);
DAC_DB <= std_ulogic_vector(cnt + 2**13);
-- ADC Section - switch off everything
ADC_CLK_A <= '0';
ADC_CLK_B <= '0';
ADC_OEB_A <= '1';
ADC_OEB_B <= '1';
POWER_ON <= '1';
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
entity t_de1_seq is
end;
architecture tbench of t_de1_seq is
component de1_seq is
port ( CLOCK_50 : in std_ulogic;
SW : in std_ulogic_vector(3 downto 0);
KEY0 : in std_ulogic;
EXP_PIN2 : out std_ulogic;
EXP_PIN4 : out std_ulogic;
EXP_PIN6 : out std_ulogic;
LEDR : out std_ulogic_vector(9 downto 0)); -- red LEDs
end component;
signal redleds : std_ulogic_vector(9 downto 0);
signal clk, rst_n : std_ulogic;
signal simstop : boolean := false;
signal exp2, exp4, exp6 : std_ulogic;
signal schalter : std_ulogic_vector(3 downto 0) := "0000";
begin
de1_seq_i0 : de1_seq
port map (
CLOCK_50 => clk,
SW => schalter,
KEY0 => rst_n,
EXP_PIN2 => exp2,
EXP_PIN4 => exp4,
EXP_PIN6 => exp6,
LEDR => redleds);
rst_n <= '1', '0' after 20 ns, '1' after 40 ns;
clk_p : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if simstop then
wait;
end if;
end process clk_p;
-- This is the process where the switches are switched.
schalter_p : process
begin
wait for 100 us;
simstop <= true;
wait;
end process schalter_p;
end; -- architecture
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment