Copied from Digitaltechnik Praktikum git.

.gitignore

+# Ignore files for git
+
+# Emacs backup files
+*~
+*.bak
+

README.md

+Praktikum Digitaltechnik
+========================
+
+Im Rahmen des Praktikums Digitaltechnik wird eine Schrittmotorsteuerung entworfen. In jedem Praktikumsversuch wird eine neue Komponente fuer die Steuerung vorgestellt. 
+
+  * Multiplexer
+  * Binaer zu 7Segment Konverter
+  * Addierer
+  * Zaehler
+  * Flankenerkennung
+  * Zustandsautomat zur Auswertung eines Drehgebers
+  * Ansteuerung Schrittmotor
+  
+Technische Umsetzung
+--------------------
+
+### Entwicklungsumgebung
+
+Die Schaltungsteile sind in VHDL beschrieben. Als FPGA Board
+wird das Altera DE1 Board verwendet. Die Designsoftware ist kostenlos von Altera erhaeltlich. 
+
+  * Synthese: Altera Quartus II
+  * Simulation: Altera Mentor Modelsim (Web Edition)
+
+Die Designsoftware ist auf einer virtuellen Maschine fertig installiert. Eine Beschreibung ist hier: http://www.hs-augsburg.de/~beckmanf/dokuwiki/doku.php?id=ubuntu_virtual_cae_system
+
+### Ordnerstruktur
+
+src: hier sind alle VHDL Quelldateien
+sim: hier sind die Makefiles fuer die Simulation der Komponenten
+pnr: Place and Route - Die makefiles fuer die Synthese der Schaltung
+scripts: Globale scripts
+
+### Download, Simulation und Synthese 
+
+Das Projekt ist unter git Versionsverwaltung. Zum Download sind die folgenden Schritte notwendig: 
+
+```
+mkdir projects
+cd projects
+git clone git@git.etech.fh-augsburg.de:friedrich.beckmann/digitaltechnikpraktikum.git
+cd digitaltechnikpraktikum
+```
+
+Hier die Simulation des Multiplexers:
+
+```
+cd sim
+cd mux2to1
+make sim
+```
+
+Um den Multiplexer zu synthetisieren:
+
+```
+cd ../../pnr
+cd de1_mux2to1
+make compile
+```
+
+Um das Design auf das Board zu laden muss das Board mit dem Kabel an den USB Anschluss des Rechners angeschlossen sein. Dann:
+
+```
+make prog
+```
+
+Ein einfaches make zeigt die moeglichen Targets. 
+
+
+
+
+
+

doc/ReadMe.md

+VLSI Design Project Directory Structure
+=======================================
+
+  -----------------------------------------------------------------------------
+  Author(s)  : 
+  johann.faerber@hs-augsburg.de, friedrich.beckmann@hs-augsburg.de
+  -----------------------------------------------------------------------------
+  Company    : 
+  University of Applied Sciences Augsburg
+  -----------------------------------------------------------------------------
+  Description: 
+  This VLSI Design Project Directory Structure using makefiles
+  allows automating design flow for frontend tools
+  like ModelSim and backend tools like Altera Quartus
+  -----------------------------------------------------------------------------
+
+
+Design Flow
+-----------
+A simplified design flow consists of
+
+  * Design Creation
+  * Functional Verification
+  * Synthesis, Physical Design, Manufacture
+  * Prototype Test
+
+Makefile Targets for Verification
+---------------------------------
+The corresponding targets to the design flow for the functional verification
+of a design with ModelSim are:
+
+```
+  "make mproject" to create a new modelsim project
+  "make compile" to compile all VHDL sources in batch mode
+  "make sim" to start modelsim gui with the top testbench of the project
+  "make modelsim" to start modelsim with graphical user interface
+  "make clean" to remove all generated files
+```
+
+e.g.
+To start the graphical user interface of the ModelSim simulator with
+the corresponding project, use the following command sequence:
+
+```
+cd sim/mux2to1
+make sim
+```
+
+Makefile Targets for Synthesis
+------------------------------
+The corresponding targets to the design flow for synthesis, physical design,
+manufacture of a design with Altera Quartus are:
+
+```
+  "make qproject" to create a new quartus project
+  "make compile" synthesize the design
+  "make prog" to configure programmable device
+  "make quartus" to start quartus graphical user interface
+  "make clean" to remove all generated files
+```
+
+e.g.  
+To configure an FPGA on a connected prototype board with
+the corresponding project, use the following command sequence:
+
+```
+cd pnr/mux2to1
+make prog
+```
+
+Naming Conventions
+------------------
+The overall makefile for simulation is located in
+
+sim/makefile
+
+The top level entity of a subdesign is assigned as the project name for verification
+in the makefile, e.g.
+
+sim/mux2to1/makefile
+
+```
+# Project name for simulation
+PROJECT = mux2to1
+```
+
+The corresponding testbench is assumed t_top_level_entity.vhd,
+e.g. t_mux2to1.vhd and assigned in the makefile as well:
+
+```
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+```
+
+
+The overall makefile for synthesis is located in
+
+pnr/makefile
+
+A similar convention for a subdesign is used for synthesis, physical design,
+manufacture in the makefile, e.g. using a DE1 prototype board
+
+pnr/de1_mux2to1/makefile
+
+```
+# Project name for simulation
+SIM_PROJECT_NAME = mux2to1
+# Project name for synthesis, physical design, manufacture
+PROJECT = de1_$(SIM_PROJECT_NAME)
+```
+
+The corresponding top level is assumed de1_top_level_entity_structure.vhd,
+e.g. de1_mux2to1_structure.vhd and assigned in the makefile as well:
+
+```
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+```
+
+Project Directory Structure
+---------------------------
+Automated design flow with makefile relies on the following directory structure:
+
+```  
+   VLSIDesignOverallProjectName
+   |   
+   +---src
+   |       and2gate_equation.vhd
+   |       invgate_equation.vhd
+   |       mux2to1_structure.vhd
+   |       or2gate_equation.vhd
+   |       t_mux2to1.vhd
+   |       de1_mux2to1_structure.vhd
+   |
+   +---sim
+   |   |   makefile
+   |   |
+   |   \---mux2to1
+   |           makefile
+   |           makefile.sources
+   |
+   +---pnr
+   |   |   makefile
+   |   |
+   |   \---de1_mux2to1
+   |           de1_mux2to1_pins.tcl
+   |           makefile
+   |
+   +---scripts
+   |       de1_pin_assignments_minimumio.csv
+   |       de1_pin_assignments_minimumio.tcl
+   |       modelsim.ini
+   |       quartus_project_settings.tcl
+   |
+   \---doc
+           ReadMe.md
+```

pnr/de1_add4/de1_add4_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_J2  -to HEX0[0]
+set_location_assignment PIN_J1  -to HEX0[1]
+set_location_assignment PIN_H2  -to HEX0[2]
+set_location_assignment PIN_H1  -to HEX0[3]
+set_location_assignment PIN_F2  -to HEX0[4]
+set_location_assignment PIN_F1  -to HEX0[5]
+set_location_assignment PIN_E2  -to HEX0[6]
+set_location_assignment PIN_E1  -to HEX1[0]
+set_location_assignment PIN_H6  -to HEX1[1]
+set_location_assignment PIN_H5  -to HEX1[2]
+set_location_assignment PIN_H4  -to HEX1[3]
+set_location_assignment PIN_G3  -to HEX1[4]
+set_location_assignment PIN_D2  -to HEX1[5]
+set_location_assignment PIN_D1  -to HEX1[6]
+set_location_assignment PIN_G5  -to HEX2[0]
+set_location_assignment PIN_G6  -to HEX2[1]
+set_location_assignment PIN_C2  -to HEX2[2]
+set_location_assignment PIN_C1  -to HEX2[3]
+set_location_assignment PIN_E3  -to HEX2[4]
+set_location_assignment PIN_E4  -to HEX2[5]
+set_location_assignment PIN_D3  -to HEX2[6]
+
+
+

pnr/de1_add4/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = de1_add4
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/de1_blinklicht/de1_blinklicht_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R22 -to KEY[0] 
+set_location_assignment PIN_R21 -to KEY[1] 
+set_location_assignment PIN_T22 -to KEY[2] 
+set_location_assignment PIN_T21 -to KEY[3] 
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]

pnr/de1_blinklicht/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+
+SIM_PROJECT_NAME = de1_blinklicht
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/de1_blnkauto/de1_blnkauto_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW0
+set_location_assignment PIN_R22 -to KEY0 
+set_location_assignment PIN_L1  -to CLOCK_50   
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+

pnr/de1_blnkauto/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+
+SIM_PROJECT_NAME = de1_blnkauto
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/de1_cnt15/de1_cnt15_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R22 -to KEY[0] 
+set_location_assignment PIN_R21 -to KEY[1] 
+set_location_assignment PIN_T22 -to KEY[2] 
+set_location_assignment PIN_T21 -to KEY[3] 
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_J2  -to HEX0[0]
+set_location_assignment PIN_J1  -to HEX0[1]
+set_location_assignment PIN_H2  -to HEX0[2]
+set_location_assignment PIN_H1  -to HEX0[3]
+set_location_assignment PIN_F2  -to HEX0[4]
+set_location_assignment PIN_F1  -to HEX0[5]
+set_location_assignment PIN_E2  -to HEX0[6]
+
+
+
+
+
+
+

pnr/de1_cnt15/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+SIM_PROJECT_NAME = de1_cnt15
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/de1_flipflop/de1_flipflop_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R22 -to KEY[0] 
+set_location_assignment PIN_R21 -to KEY[1] 
+set_location_assignment PIN_T22 -to KEY[2] 
+set_location_assignment PIN_T21 -to KEY[3] 
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]

pnr/de1_flipflop/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+
+SIM_PROJECT_NAME = de1_flipflop
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/de1_majority/de1_majority_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_J2  -to HEX0[0]
+set_location_assignment PIN_J1  -to HEX0[1]
+set_location_assignment PIN_H2  -to HEX0[2]
+set_location_assignment PIN_H1  -to HEX0[3]
+set_location_assignment PIN_F2  -to HEX0[4]
+set_location_assignment PIN_F1  -to HEX0[5]
+set_location_assignment PIN_E2  -to HEX0[6]
+set_location_assignment PIN_E1  -to HEX1[0]
+set_location_assignment PIN_H6  -to HEX1[1]
+set_location_assignment PIN_H5  -to HEX1[2]
+set_location_assignment PIN_H4  -to HEX1[3]
+set_location_assignment PIN_G3  -to HEX1[4]
+set_location_assignment PIN_D2  -to HEX1[5]
+set_location_assignment PIN_D1  -to HEX1[6]
+set_location_assignment PIN_G5  -to HEX2[0]
+set_location_assignment PIN_G6  -to HEX2[1]
+set_location_assignment PIN_C2  -to HEX2[2]
+set_location_assignment PIN_C1  -to HEX2[3]
+set_location_assignment PIN_E3  -to HEX2[4]
+set_location_assignment PIN_E4  -to HEX2[5]
+set_location_assignment PIN_D3  -to HEX2[6]
+set_location_assignment PIN_F4  -to HEX3[0]
+set_location_assignment PIN_D5  -to HEX3[1]
+set_location_assignment PIN_D6  -to HEX3[2]
+set_location_assignment PIN_J4  -to HEX3[3]
+set_location_assignment PIN_L8  -to HEX3[4]
+set_location_assignment PIN_F3  -to HEX3[5]
+set_location_assignment PIN_D4  -to HEX3[6]
+
+
+
+
+
+

pnr/de1_majority/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+