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This is the simple system clock equal to data clock data
transmission with 6 Bit LFSR as Scrambler and Descrambler.

project originated from Digitaltechnik Praktikum. Removed all
files which are not required anymore.

this is the board configuration file to run fpga in the loop simulations

added the sinewave generator project setup to include
the matlab generated hdl files. The matlab files are not
part of this commit, but the makefile.sources file references
them. They are supposed to be generated from matlab.

The initial setup was for the Terasic DE1 Board with Cyclone II
fpga. This commit changes the synthesis setup to use the Cyclone V
fpga and changes the pin configuration to the DE1-SoC board.