- 26 Apr, 2017 1 commit
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Friedrich Beckmann authored
This is the simple system clock equal to data clock data transmission with 6 Bit LFSR as Scrambler and Descrambler.
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- 20 Apr, 2017 1 commit
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Friedrich Beckmann authored
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- 19 Apr, 2017 2 commits
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Friedrich Beckmann authored
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Friedrich Beckmann authored
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- 06 Apr, 2017 3 commits
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Friedrich Beckmann authored
project originated from Digitaltechnik Praktikum. Removed all files which are not required anymore.
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Friedrich Beckmann authored
this is the board configuration file to run fpga in the loop simulations
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Friedrich Beckmann authored
added the sinewave generator project setup to include the matlab generated hdl files. The matlab files are not part of this commit, but the makefile.sources file references them. They are supposed to be generated from matlab.
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- 31 Mar, 2017 1 commit
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Friedrich Beckmann authored
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- 30 Mar, 2017 2 commits
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Friedrich Beckmann authored
The initial setup was for the Terasic DE1 Board with Cyclone II fpga. This commit changes the synthesis setup to use the Cyclone V fpga and changes the pin configuration to the DE1-SoC board.
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Friedrich Beckmann authored
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