Commit 1313c56c authored by Aaron Erhardt's avatar Aaron Erhardt
Browse files

Fix typos


Signed-off-by: default avatarAaron Erhardt <aaron.erhardt@t-online.de>
parent c4e5e149
Pipeline #704 passed with stage
in 1 minute and 48 seconds
......@@ -5,33 +5,33 @@
### Add
```asm
add r0, r1, r2 ; ro = r1 + r2
add r0, r1 ; ro = r0 + r1
add r0, #1 ; ro = r0 + 1, for small constants
add r0, r1, r2 ; r0 = r1 + r2
add r0, r1 ; r0 = r0 + r1
add r0, #1 ; r0 = r0 + 1, for small constants
```
Set flags while adding
```asm
adds r0, r1, r2 ; ro = r1 + r2, also sets flags
adds r0, r1, r2 ; r0 = r1 + r2, also sets flags
```
### Subtract
```asm
sub r0, r1, r2 ; ro = r1 - r2
sub r0, r1, r2 ; r0 = r1 - r2
```
### Multiply
```asm
mul r0, r1, r2 ; ro = r1 * r2
mul r0, r1, r2 ; r0 = r1 * r2
```
### Divide
```asm
udiv r0, r1, r2 ; ro = r1 / r2, unsigned divide, always rounds down
udiv r0, r1, r2 ; r0 = r1 / r2, unsigned divide, always rounds down
```
## Logic
......@@ -39,19 +39,19 @@ udiv r0, r1, r2 ; ro = r1 / r2, unsigned divide, always rounds down
### And
```asm
and r0, r1, r2 ; ro = r1 AND r2
and r0, r1, r2 ; r0 = r1 AND r2
```
### OR
```asm
orr r0, r1, r2 ; ro = r1 OR r2
orr r0, r1, r2 ; r0 = r1 OR r2
```
### Exclusive or
```asm
eor r0, r1, r2 ; ro = r1 XOR r2
eor r0, r1, r2 ; r0 = r1 XOR r2
```
......@@ -60,25 +60,25 @@ eor r0, r1, r2 ; ro = r1 XOR r2
### Arithmetic shift right
```asm
asr r0, r1, r2 ; ro = r1 >> r2, keeps correct sign!
asr r0, r1, r2 ; r0 = r1 >> r2, keeps correct sign!
```
### Logical shift right
```asm
lsr r0, r1, r2 ; ro = r1 >> r2, fills with zeros and doesn't keep correct sign!
lsr r0, r1, r2 ; r0 = r1 >> r2, fills with zeros and doesn't keep correct sign!
```
### Logical shift left
```asm
lsl r0, r1, r2 ; ro = r1 << r2, fills with zeros
lsl r0, r1, r2 ; r0 = r1 << r2, fills with zeros
```
### Rotate right
```asm
ror r0, r1, r2 ; ro = r1 >> r2, bits will wrap around
ror r0, r1, r2 ; r0 = r1 >> r2, bits will wrap around
```
## Load
......
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