Commit 9d6cb676 authored by Aaron Erhardt's avatar Aaron Erhardt
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Microcomputertechnik lecture 18.5


Signed-off-by: default avatarAaron Erhardt <aaron.erhardt@t-online.de>
parent b2fe8b91
Pipeline #587 passed with stage
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......@@ -381,10 +381,68 @@ Maskable interrupts can be explicitly enabled or disabled. Not maskable interrup
### Concurrent interrupts
**Daisy Chain (forward IntAck in a chain)**
#### Daisy Chain (forward IntAck in a chain)
+ Connect IRQ with logical OR
+ IntAck is only sent to one I/O-block.
+ Each block only forwards IntAck if it doesn't want to run an interrupt itself.
+ This creates a (geographically) prioritized chain that guarantees that only one interrupt is executed at a time
#### Interrupt level
+ Each I/O-block has it's own prioritized IRQ connection and IntAck connection to the CPU
+ CPU decides which IRQ signal is more important with a hard coded mask
+ IntEnable is more than one bit
+ Nested interrupts (interrupts interrupting each other) are possible
#### Interrupt controller
+ I/O-blocks are connected to an interrupt controller that decides which vector number is forwarded
+ Interrupt controller sends IRQ to the CPU and puts the selected vector number on the bus
### Interrupts in Cortex M3/4
#### Vectortable
+ Table storing 32-bit addresses to interrupt and exception routines
+ First part (0-15, defined by CPU type): Reserved for system exception routines
+ Second part (16-255, defined by design of micro controller): reserved for interrupts by I/O-blocks
#### Nested Vectored Interrupt Controller (NVIC)
+ Maps IRQ signal by I/O-blocks to vector numbers
+ Is part of the CPU and contains the systick timer
+ I/O-block only sends IRQ if IntEnable bit was set, then NVIC decides whether the interrupt should be handled and then the CPU checks whether the priority is high enough
#### Mask register
+ PRIMASK register: 1-bit, can disable all interrupts except NMI (not maskable interrupts) and hard-fault
+ FAULTMASK register: 1-bit, can disable all interrupts except NMI
+ BASEPRI register: 8-bit (only first 4 bit are used), disables interrupts with equal or lower priority (low number => high priority!!!)
+ Only accessible with special move commands (for supervisor mode):
+ MRS: special register -> register
+ MSR: register -> special register
#### NVIC registers
+ Register are blocks of 3x32-bit = 96 bits
+ Interrupt Set Enable: Enable interrupt by setting a specific bit
+ Interrupt Clear Enable: Disable interrupt by setting a specific bit
+ Interrupt Set Pending: Shows which interrupts are currently pending
+ Interrupt Clear Pending: Allows clearing pending status of an interrupt
+ Active Status: Show which interrupt(s) is/are currently executed
+ Priority: Table of 8-bit priorities for interrupts
#### Preparing an interrupt
+ Write interrupt routine addresses into the vector table
+ Set priority of interrupt in NVIC
+ Enable interrupt in NVIC (Interrupt Set Enable register)
+ Set IntEnable bit of I/O-block
#### Interrupt running order
1. Pending state: Interrupt Set Pending register bit is set (and can be removed by software). This bits remains set until interrupt is executed.
2. Jump to interrupt service routine (ISR). CPU saves PSR (status register), PC, LR, r0-r3 and r12 on the stack.
3. PSR is set to interrupt number and the Active Status register bit is set.
4. Interrupt service routine is executed. Further registers can be pushed to the stack. ISR in finished with `bx lr`. Automatically pushed registers are popped.
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