Commit c4e5e149 authored by Aaron Erhardt's avatar Aaron Erhardt
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Add system bus chapter


Signed-off-by: default avatarAaron Erhardt <aaron.erhardt@t-online.de>
parent 9d6cb676
......@@ -445,4 +445,55 @@ Maskable interrupts can be explicitly enabled or disabled. Not maskable interrup
1. Pending state: Interrupt Set Pending register bit is set (and can be removed by software). This bits remains set until interrupt is executed.
2. Jump to interrupt service routine (ISR). CPU saves PSR (status register), PC, LR, r0-r3 and r12 on the stack.
3. PSR is set to interrupt number and the Active Status register bit is set.
4. Interrupt service routine is executed. Further registers can be pushed to the stack. ISR in finished with `bx lr`. Automatically pushed registers are popped.
\ No newline at end of file
4. Interrupt service routine is executed. Further registers can be pushed to the stack. ISR in finished with `bx lr`. Automatically pushed registers are popped.
# C programming
## volatile keyword
Indicates to the compiler that it shouldn't optimize reads and writes to a variable. This is necessary for accessing registers or for multi threaded programs.
## Interrupt routines
```C
// Interrupt routines can't return not take arguments
void interrupt_handler(void) {
// code...
}
```
## Inline assembler
```C
register int BASEPRI __asm("basepri");
__asm void wait(void) {
push {r0, r1}
// ...
bx lr
}
```
# System bus
* Address bus
+ Data bus
+ Control bus
### Synchronous system bus
The slowest block connected to the bus defines the clock frequency for the whole bus -> slow.
### Asynchronous system bus
Additional signals are transmitted to indicate successful data transfer. The bus can be as fast as the currently involved blocks allow it.
Additional handshake signals required:
+ Address strobe (AS) -> address is valid
+ Data strobe (DS) -> data is valid
+ Data transfer acknowledge (DTACK) -> data transferred
In reality /DTACK isn't activated by a responding block but rather by a delay connected to /CS (chip select) that corresponds to the blocks response time. If no block responds to the CPU because an invalid address was used an additional longer delay emits a signal to /BERR to indicate a bus error to the CPU.
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