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README.md

+Entwurf digitaler Systeme 1
+===========================
+
+Im Rahmen der Veranstaltung Entwurf digitaler Systeme 1 werden einige digitale Systeme entworfen.
+
+  * VGA Bildgenerator
+  * serielle Binär zu BCD Umwandlung
+  
+Technische Umsetzung
+--------------------
+
+### Entwicklungsumgebung
+
+Die Schaltungsteile sind in VHDL beschrieben. Als FPGA Board
+wird das Altera DE1 Board verwendet. Die Designsoftware ist kostenlos von Altera erhaeltlich. 
+
+  * Synthese: Altera Quartus II
+  * Simulation: Altera Mentor Modelsim (Web Edition)
+
+Die Designsoftware ist auf einer virtuellen Maschine fertig installiert. Eine Beschreibung ist hier: http://www.hs-augsburg.de/~beckmanf/dokuwiki/doku.php?id=ubuntu_virtual_cae_system
+
+### Ordnerstruktur
+
+  * src: hier sind alle VHDL Quelldateien
+  * sim: hier sind die Makefiles fuer die Simulation der Komponenten
+  * pnr: Place and Route - Die makefiles fuer die Synthese der Schaltung
+  * scripts: Globale scripts
+
+### Download, Simulation und Synthese 
+
+Das Projekt ist unter git Versionsverwaltung. Für den Zugriff auf den git server der Hochschule über das git Protokoll müssen Sie im VPN sein. Zum Download sind die folgenden Schritte notwendig: 
+
+```
+mkdir projects
+cd projects
+git clone https://gitlab.elektrotechnik.hs-augsburg.de/beckmanf/eds1.git
+cd eds1
+```
+
+Simulationstest:
+
+```
+cd sim
+cd bin2bcd
+make sim
+```
+
+Synthesetest:
+
+```
+cd ../../pnr
+cd de1_meta
+make compile
+```
+
+Um das Design auf das Board zu laden muss das Board mit dem Kabel an den USB Anschluss des Rechners angeschlossen sein. Dann:
+
+```
+make prog
+```
+
+Ein einfaches make zeigt die moeglichen Targets.

doc/ReadMe.md

+VLSI Design Project Directory Structure
+=======================================
+
+  -----------------------------------------------------------------------------
+  Author(s)  : 
+  johann.faerber@hs-augsburg.de, friedrich.beckmann@hs-augsburg.de
+  -----------------------------------------------------------------------------
+  Company    : 
+  University of Applied Sciences Augsburg
+  -----------------------------------------------------------------------------
+  Description: 
+  This VLSI Design Project Directory Structure using makefiles
+  allows automating design flow for frontend tools
+  like ModelSim and backend tools like Altera Quartus
+  -----------------------------------------------------------------------------
+
+
+Design Flow
+-----------
+A simplified design flow consists of
+
+  * Design Creation
+  * Functional Verification
+  * Synthesis, Physical Design, Manufacture
+  * Prototype Test
+
+Makefile Targets for Verification
+---------------------------------
+The corresponding targets to the design flow for the functional verification
+of a design with ModelSim are:
+
+```
+  "make mproject" to create a new modelsim project
+  "make compile" to compile all VHDL sources in batch mode
+  "make sim" to start modelsim gui with the top testbench of the project
+  "make modelsim" to start modelsim with graphical user interface
+  "make clean" to remove all generated files
+```
+
+e.g.
+To start the graphical user interface of the ModelSim simulator with
+the corresponding project, use the following command sequence:
+
+```
+cd sim/mux2to1
+make sim
+```
+
+Makefile Targets for Synthesis
+------------------------------
+The corresponding targets to the design flow for synthesis, physical design,
+manufacture of a design with Altera Quartus are:
+
+```
+  "make qproject" to create a new quartus project
+  "make compile" synthesize the design
+  "make prog" to configure programmable device
+  "make quartus" to start quartus graphical user interface
+  "make clean" to remove all generated files
+```
+
+e.g.  
+To configure an FPGA on a connected prototype board with
+the corresponding project, use the following command sequence:
+
+```
+cd pnr/mux2to1
+make prog
+```
+
+Naming Conventions
+------------------
+The overall makefile for simulation is located in
+
+sim/makefile
+
+The top level entity of a subdesign is assigned as the project name for verification
+in the makefile, e.g.
+
+sim/mux2to1/makefile
+
+```
+# Project name for simulation
+PROJECT = mux2to1
+```
+
+The corresponding testbench is assumed t_top_level_entity.vhd,
+e.g. t_mux2to1.vhd and assigned in the makefile as well:
+
+```
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+```
+
+
+The overall makefile for synthesis is located in
+
+pnr/makefile
+
+A similar convention for a subdesign is used for synthesis, physical design,
+manufacture in the makefile, e.g. using a DE1 prototype board
+
+pnr/de1_mux2to1/makefile
+
+```
+# Project name for simulation
+SIM_PROJECT_NAME = mux2to1
+# Project name for synthesis, physical design, manufacture
+PROJECT = de1_$(SIM_PROJECT_NAME)
+```
+
+The corresponding top level is assumed de1_top_level_entity_structure.vhd,
+e.g. de1_mux2to1_structure.vhd and assigned in the makefile as well:
+
+```
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_structure.vhd
+```
+
+Project Directory Structure
+---------------------------
+Automated design flow with makefile relies on the following directory structure:
+
+```  
+   VLSIDesignOverallProjectName
+   |   
+   +---src
+   |       and2gate_equation.vhd
+   |       invgate_equation.vhd
+   |       mux2to1_structure.vhd
+   |       or2gate_equation.vhd
+   |       t_mux2to1.vhd
+   |       de1_mux2to1_structure.vhd
+   |
+   +---sim
+   |   |   makefile
+   |   |
+   |   \---mux2to1
+   |           makefile
+   |           makefile.sources
+   |
+   +---pnr
+   |   |   makefile
+   |   |
+   |   \---de1_mux2to1
+   |           de1_mux2to1_pins.tcl
+   |           makefile
+   |
+   +---scripts
+   |       de1_pin_assignments_minimumio.csv
+   |       de1_pin_assignments_minimumio.tcl
+   |       modelsim.ini
+   |       quartus_project_settings.tcl
+   |
+   \---doc
+           ReadMe.md
+```

pnr/de1_meta/de1_meta_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27
+set_location_assignment PIN_L1  -to CLOCK_50  
+set_location_assignment PIN_R22 -to KEY[0] 
+set_location_assignment PIN_R21 -to KEY[1] 
+set_location_assignment PIN_T22 -to KEY[2] 
+set_location_assignment PIN_T21 -to KEY[3] 
+
+

pnr/de1_meta/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+SIM_PROJECT_NAME = de1_meta
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/de1_sermul/de1_sermul_pins.tcl

+# Pin Configuration 
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2  -to SW[7]
+set_location_assignment PIN_M1  -to SW[8]
+set_location_assignment PIN_L2  -to SW[9]
+set_location_assignment PIN_R22 -to KEY[0] 
+set_location_assignment PIN_R21 -to KEY[1] 
+set_location_assignment PIN_T22 -to KEY[2] 
+set_location_assignment PIN_T21 -to KEY[3] 
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_location_assignment PIN_J2  -to HEX0[0]
+set_location_assignment PIN_J1  -to HEX0[1]
+set_location_assignment PIN_H2  -to HEX0[2]
+set_location_assignment PIN_H1  -to HEX0[3]
+set_location_assignment PIN_F2  -to HEX0[4]
+set_location_assignment PIN_F1  -to HEX0[5]
+set_location_assignment PIN_E2  -to HEX0[6]
+set_location_assignment PIN_E1  -to HEX1[0]
+set_location_assignment PIN_H6  -to HEX1[1]
+set_location_assignment PIN_H5  -to HEX1[2]
+set_location_assignment PIN_H4  -to HEX1[3]
+set_location_assignment PIN_G3  -to HEX1[4]
+set_location_assignment PIN_D2  -to HEX1[5]
+set_location_assignment PIN_D1  -to HEX1[6]
+set_location_assignment PIN_G5  -to HEX2[0]
+set_location_assignment PIN_G6  -to HEX2[1]
+set_location_assignment PIN_C2  -to HEX2[2]
+set_location_assignment PIN_C1  -to HEX2[3]
+set_location_assignment PIN_E3  -to HEX2[4]
+set_location_assignment PIN_E4  -to HEX2[5]
+set_location_assignment PIN_D3  -to HEX2[6]
+set_location_assignment PIN_F4  -to HEX3[0]
+set_location_assignment PIN_D5  -to HEX3[1]
+set_location_assignment PIN_D6  -to HEX3[2]
+set_location_assignment PIN_J4  -to HEX3[3]
+set_location_assignment PIN_L8  -to HEX3[4]
+set_location_assignment PIN_F3  -to HEX3[5]
+set_location_assignment PIN_D4  -to HEX3[6]
+

pnr/de1_sermul/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = de1_sermul
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure shown at 
+##              the end of this file.
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Main Targets
+#
+###################################################################
+
+help:
+	@echo '"make" does intentionally nothing. Type:'
+	@echo '  "make qproject" to create quartus project only'
+	@echo '  "make compile" to synthesize the design'
+	@echo '  "make prog" to configure programmable device'
+	@echo '  "make quartus" to start quartus graphical user interface'
+	@echo '  "make clean" to remove all generated files'
+
+
+qproject: $(PROJECT).qpf
+
+$(PROJECT).qpf: $(SOURCE_FILES) ../../scripts/create_quartus_project_settings.tcl $(PROJECT)_pins.tcl ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+	# assign VHDL design files
+	rm -rf quartus_vhdl_source_files.tcl
+	for source_file in $(SOURCE_FILES); do \
+		echo set_global_assignment -name VHDL_FILE $$source_file >> quartus_vhdl_source_files.tcl; \
+	done
+	# just create a quartus project
+	quartus_sh -t ../../scripts/create_quartus_project_settings.tcl -projectname $(PROJECT)
+
+
+compile: flowsummary.log
+
+flowsummary.log: $(PROJECT).qpf ../../scripts/quartus_project_flow.tcl
+	quartus_sh -t ../../scripts/quartus_project_flow.tcl -projectname $(PROJECT) 
+
+prog: flowsummary.log
+	quartus_pgm -c USB-Blaster --mode jtag --operation="p;$(PROJECT).sof"
+
+quartus: $(PROJECT).qpf
+	# start	quartus gui
+	quartus $(PROJECT).qpf &
+
+clean:
+	rm -rf *~ *.rpt *.chg *.log quartus_vhdl_source_files.tcl *.htm *.eqn *.pin *.sof *.pof db incremental_db *.qpf *.qsf *.summary $(PROJECT).* 
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+

pnr/mem/makefile

+SIM_PROJECT_NAME = mem
+PROJECT = $(SIM_PROJECT_NAME)
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/mem/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) 
+
+include ../makefile
+
+

pnr/mem/mem_pins.tcl

+# Pin Configuration 
+

scripts/create_quartus_project_settings.tcl

+## ----------------------------------------------------------------------------
+## Script     : create_quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, F. Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: create a quartus project with default settings for device, 
+##              unused pins, ...
+##              expects project name as command line parameter 
+##              It expects one file containing the vhdl source files and
+##              one file containing the pin constraints. 
+##              Start with
+##              quartus_sh -t create_quartus_project_settings.tcl -projectname de1_mux2to1
+
+package require cmdline
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+# ----------------------------------------------------------------------------
+# Declare command line parameters
+# ----------------------------------------------------------------------------
+set parameters {
+    {projectname.arg ""   "Project Name"}
+}
+array set arg [::cmdline::getoptions argv $parameters]
+
+# ----------------------------------------------------------------------------
+# Verify required paramters
+# ----------------------------------------------------------------------------
+set requiredParameters {projectname}
+foreach parameter $requiredParameters {
+    if {$arg($parameter) == ""} {
+        puts stderr "Missing required parameter: -$parameter"
+        exit 1
+    }
+}
+
+
+	# ----------------------------------------------------------------------------
+	# Create project
+	# ----------------------------------------------------------------------------
+	project_new $arg(projectname) -overwrite
+	
+	# ----------------------------------------------------------------------------
+	# Assign family, device, and top-level file
+	# ----------------------------------------------------------------------------
+	set_global_assignment -name FAMILY "Cyclone II"
+	set_global_assignment -name DEVICE EP2C20F484C7
+	
+	# ----------------------------------------------------------------------------
+	# Default settings
+	# ----------------------------------------------------------------------------
+	set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+	set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+	set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+	
+	# ----------------------------------------------------------------------------
+	# Design files
+	# ----------------------------------------------------------------------------
+	#set_global_assignment -name VHDL_FILE ../src/e_cntdnmodm.vhd
+	#set_global_assignment -name VHDL_FILE ../src/a_cntdnmodm_rtl.vhd
+        # The following file is generated by the make process and contains
+        # the vhdl files which belong to the project
+        source quartus_vhdl_source_files.tcl
+	
+	# ----------------------------------------------------------------------------
+	# Pin Assignments
+	# ----------------------------------------------------------------------------
+	# set_location_assignment PIN_L1 -to CLOCK_50
+	source $arg(projectname)_pins.tcl 
+
+	# ----------------------------------------------------------------------------
+	# Close project
+	# ----------------------------------------------------------------------------
+	project_close
+
+

scripts/de1_pin_assignments_minimumio.csv

+# This are all pin location assignments derived from the CDROM file
+# Friedrich Beckmann, 27.3.2014
+
+To,Location
+GPIO_0[0],PIN_A13
+GPIO_0[1],PIN_B13
+GPIO_0[2],PIN_A14
+GPIO_0[3],PIN_B14
+GPIO_0[4],PIN_A15
+GPIO_0[5],PIN_B15
+GPIO_0[6],PIN_A16
+GPIO_0[7],PIN_B16
+GPIO_0[8],PIN_A17
+GPIO_0[9],PIN_B17
+GPIO_0[10],PIN_A18
+GPIO_0[11],PIN_B18
+GPIO_0[12],PIN_A19
+GPIO_0[13],PIN_B19
+GPIO_0[14],PIN_A20
+GPIO_0[15],PIN_B20
+GPIO_0[16],PIN_C21
+GPIO_0[17],PIN_C22
+GPIO_0[18],PIN_D21
+GPIO_0[19],PIN_D22
+GPIO_0[20],PIN_E21
+GPIO_0[21],PIN_E22
+GPIO_0[22],PIN_F21
+GPIO_0[23],PIN_F22
+GPIO_0[24],PIN_G21
+GPIO_0[25],PIN_G22
+GPIO_0[26],PIN_J21
+GPIO_0[27],PIN_J22
+GPIO_0[28],PIN_K21
+GPIO_0[29],PIN_K22
+GPIO_0[30],PIN_J19
+GPIO_0[31],PIN_J20
+GPIO_0[32],PIN_J18
+GPIO_0[33],PIN_K20
+GPIO_0[34],PIN_L19
+GPIO_0[35],PIN_L18
+GPIO_1[0],PIN_H12
+GPIO_1[1],PIN_H13
+GPIO_1[2],PIN_H14
+GPIO_1[3],PIN_G15
+GPIO_1[4],PIN_E14
+GPIO_1[5],PIN_E15
+GPIO_1[6],PIN_F15
+GPIO_1[7],PIN_G16
+GPIO_1[8],PIN_F12
+GPIO_1[9],PIN_F13
+GPIO_1[10],PIN_C14
+GPIO_1[11],PIN_D14
+GPIO_1[12],PIN_D15
+GPIO_1[13],PIN_D16
+GPIO_1[14],PIN_C17
+GPIO_1[15],PIN_C18
+GPIO_1[16],PIN_C19
+GPIO_1[17],PIN_C20
+GPIO_1[18],PIN_D19
+GPIO_1[19],PIN_D20
+GPIO_1[20],PIN_E20
+GPIO_1[21],PIN_F20
+GPIO_1[22],PIN_E19
+GPIO_1[23],PIN_E18
+GPIO_1[24],PIN_G20
+GPIO_1[25],PIN_G18
+GPIO_1[26],PIN_G17
+GPIO_1[27],PIN_H17
+GPIO_1[28],PIN_J15
+GPIO_1[29],PIN_H18
+GPIO_1[30],PIN_N22
+GPIO_1[31],PIN_N21
+GPIO_1[32],PIN_P15